test_compldst_multi_mmu.py: use nmigen.back.pysim
[soc.git] / src / soc / fu / trap / pipe_data.py
1 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
2 from soc.fu.trap.trap_input_record import CompTrapOpSubset
3
4
5 class TrapInputData(FUBaseData):
6 regspec = [('INT', 'ra', '0:63'), # RA
7 ('INT', 'rb', '0:63'), # RB/immediate
8 ('FAST', 'fast1', '0:63'), # SRR0
9 ('FAST', 'fast2', '0:63'), # SRR1
10 ('FAST', 'fast3', '0:63'), # SVSRR0
11 # note here that MSR CIA and SVSTATE are *not* read as regs:
12 # they are passed in as incoming "State", via the
13 # CompTrapOpSubset
14 ]
15 def __init__(self, pspec):
16 super().__init__(pspec, False)
17 # convenience
18 self.srr0, self.srr1, self.svsrr0 = self.fast1, self.fast2, self.fast3
19 self.a, self.b = self.ra, self.rb
20
21
22 class TrapOutputData(FUBaseData):
23 regspec = [('INT', 'o', '0:63'), # RA
24 ('FAST', 'fast1', '0:63'), # SRR0 SPR
25 ('FAST', 'fast2', '0:63'), # SRR1 SPR
26 ('FAST', 'fast3', '0:63'), # SRR2 SPR
27 # ... however we *do* need to *write* MSR, NIA, SVSTATE (RFID)
28 ('STATE', 'nia', '0:63'), # NIA (Next PC)
29 ('STATE', 'msr', '0:63'), # MSR
30 ('STATE', 'svstate', '0:63')] # SVSTATE
31 def __init__(self, pspec):
32 super().__init__(pspec, True)
33 # convenience
34 self.srr0, self.srr1, self.svsrr0 = self.fast1, self.fast2, self.fast3
35
36
37
38 class TrapPipeSpec(CommonPipeSpec):
39 regspec = (TrapInputData.regspec, TrapOutputData.regspec)
40 opsubsetkls = CompTrapOpSubset