src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6 """
   7 from nmigen import Elaboratable, Module, Signal
   8 from nmigen.cli import rtlil
   9
  10 from soc.fu.compunits.compunits import AllFunctionUnits
  11 from soc.regfile.regfiles import RegFiles
  12 from soc.decoder.power_decoder import create_pdecode
  13 from soc.decoder.power_decoder2 import PowerDecode2
  14
  15
  16 class NonProductionCore(Elaboratable):
  17     def __init__(self):
  18         self.fus = AllFunctionUnits()
  19         self.regs = RegFiles()
  20         self.pdecode = pdecode = create_pdecode()
  21         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  22         self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27
  28         m.submodules.pdecode2 = dec2 = self.pdecode2
  29         m.submodules.fus = self.fus
  30         self.regs.elaborate_into(m, platform)
  31         regs = self.regs
  32         fus = self.fus.fus
  33
  34         # dictionary of lists of regfile read ports
  35         byregfiles_rd = {}
  36         for (funame, fu) in fus.items():
  37             print ("read ports for %s" % funame)
  38             for idx in range(fu.n_src):
  39                 (regfile, regname, wid) = fu.get_in_spec(idx)
  40                 print ("    %s %s %s" % (regfile, regname, str(wid)))
  41                 rdflag, read, _ = dec2.regspecmap(regfile, regname)
  42                 if regfile not in byregfiles_rd:
  43                     byregfiles_rd[regfile] = {}
  44                 # here we start to create "lanes"
  45                 if idx not in byregfiles_rd[regfile]:
  46                     byregfiles_rd[regfile][idx] = []
  47                 fuspec = (funame, fu, regname, rdflag, read, wid)
  48                 byregfiles_rd[regfile][idx].append(fuspec)
  49
  50         # ok just print that out, for convenience
  51         for regfile, spec in byregfiles_rd.items():
  52             print ("regfile read ports:", regfile)
  53             for idx, fuspec in spec.items():
  54                 print ("  regfile read port %s lane: %d" % (regfile, idx))
  55                 for (funame, fu, regname, rdflag, read, wid) in fuspec:
  56                     print ("    ", funame, regname, wid, read, rdflag)
  57                     print ("    ", fu)
  58                     print ()
  59
  60         return m
  61
  62     def __iter__(self):
  63         yield from self.fus.ports()
  64         yield from self.pdecode2.ports()
  65         # TODO: regs
  66
  67     def ports(self):
  68         return list(self)
  69
  70
  71 if __name__ == '__main__':
  72     dut = NonProductionCore()
  73     vl = rtlil.convert(dut, ports=dut.ports())
  74     with open("non_production_core.il", "w") as f:
  75         f.write(vl)