noticed the regular pattern in all pipe_data.py (regspecs).

removed manual Input/Output Data, use regspecs to create it, in IntegerData

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index 5b9766e295397fb74c94ecf4a086e6868605599c..4039096ab4d6c8b7b4d9f247b1011d5c64a47a3d 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -6,64 +6,27 @@ from soc.decoder.power_decoder2 import Data
 
 
 class ALUInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('XER', 'xer_so', '32'),
-               ('XER', 'xer_ca', '34,45')]
+    regspec = [('INT', 'ra', '0:63'), # RA
+               ('INT', 'rb', '0:63'), # RB/immediate
+               ('XER', 'xer_so', '32'), # XER bit 32: SO
+               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.xer_so = Signal(reset_less=True) # XER bit 32: SO
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
+        super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.xer_ca
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.xer_so.eq(i.xer_so)]
-
 
 class ALUOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ca', '34,45'),
-               ('XER', 'xer_ov', '33,44'),
+               ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
+               ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
                ('XER', 'xer_so', '32')]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="stage_o")
-        self.cr_a = Data(4, name="cr_a")
-        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
-        self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
-        self.xer_so = Data(1, name="xer_so")
+        super().__init__(pspec, True)
         # convenience
         self.cr0 = self.cr_a
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.xer_ca
-        yield self.cr_a
-        yield self.xer_ov
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.cr_a.eq(i.cr_a),
-                      self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
-
 
 class ALUPipeSpec(CommonPipeSpec):
     regspec = (ALUInputData.regspec, ALUOutputData.regspec)

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 78c4f0f972807094f19159df3b8be80e4f65da6f..74edaa1f75e21a39ad9a680e79e879d97ac8493a 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -31,64 +31,33 @@ from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
 
 
 class BranchInputData(IntegerData):
-    regspec = [('FAST', 'spr1', '0:63'),
-               ('FAST', 'spr2', '0:63'),
-               ('CR', 'cr_a', '0:3'),
-               ('FAST', 'cia', '0:63')]
+    # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
+    # this involves the *decode* unit selecting the register, based
+    # on detecting the operand being bcctr, bclr or bctar
+    regspec = [('FAST', 'spr1', '0:63'), # see table above, SPR1
+               ('FAST', 'spr2', '0:63'), # see table above, SPR2
+               ('CR', 'cr_a', '0:3'),    # Condition Register(s) CR0-7
+               ('FAST', 'cia', '0:63')]  # Current Instruction Address
     def __init__(self, pspec):
-        super().__init__(pspec)
-        # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
-        # this involves the *decode* unit selecting the register, based
-        # on detecting the operand being bcctr, bclr or bctar
-
-        self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
-        self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
-        self.cr_a = Signal(4, reset_less=True)  # Condition Register(s) CR0-7
-        self.cia = Signal(64, reset_less=True)  # Current Instruction Address
+        super().__init__(pspec, False)
 
         # convenience variables.  not all of these are used at once
         self.ctr = self.spr1
         self.lr = self.tar = self.spr2
         self.cr = self.cr_a
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.spr1
-        yield self.spr2
-        yield self.cr_a
-        yield self.cia
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
-                      self.cr_a.eq(i.cr_a), self.cia.eq(i.cia)]
-
 
 class BranchOutputData(IntegerData):
     regspec = [('FAST', 'spr1', '0:63'),
                ('FAST', 'spr2', '0:63'),
                ('FAST', 'nia', '0:63')]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.spr1 = Data(64, name="spr1")
-        self.spr2 = Data(64, name="spr2")
-        self.nia = Data(64, name="nia")
+        super().__init__(pspec, True)
 
         # convenience variables.
         self.ctr = self.spr1
         self.lr = self.tar = self.spr2
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield from self.spr1
-        yield from self.spr2
-        yield from self.nia
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
-                      self.nia.eq(i.nia)]
-
 
 class BranchPipeSpec(CommonPipeSpec):
     regspec = (BranchInputData.regspec, BranchOutputData.regspec)

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 24402270c9ed0472d4a38689a3a1c6d6a807851d..00f24dbdf51c299ce806c807ce434521750fe6ee 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -15,61 +15,22 @@ class CRInputData(IntegerData):
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3'),     # 4 bit range
                ('CR', 'cr_b', '0:3'),     # 4 bit range
-               ('CR', 'cr_c', '0:3')]     # 4 bit range
+               ('CR', 'cr_c', '0:3')]     # 4 bit: for CR_OP partial update
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB
-        self.full_cr = Signal(32, reset_less=True) # full CR in
-        self.cr_a = Signal(4, reset_less=True)
-        self.cr_b = Signal(4, reset_less=True)
-        self.cr_c = Signal(4, reset_less=True) # needed for CR_OP partial update
+        super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.full_cr
-        yield self.cr_a
-        yield self.cr_b
-        yield self.cr_c
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra),
-                      self.rb.eq(i.rb),
-                      self.full_cr.eq(i.full_cr),
-                      self.cr_a.eq(i.cr_a),
-                      self.cr_b.eq(i.cr_b),
-                      self.cr_c.eq(i.cr_c)]
-                      
 
 class CROutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),      # 64 bit range
+    regspec = [('INT', 'o', '0:63'),      # RA - 64 bit range
                ('CR', 'full_cr', '0:31'), # 32 bit range
                ('CR', 'cr_a', '0:3')]     # 4 bit range
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="o") # RA
-        self.full_cr = Data(32, name="full_cr")
-        self.cr_a = Data(4, name="cr_a")
+        super().__init__(pspec, True)
         # convenience
         self.cr = self.cr_a
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.full_cr
-        yield self.cr_a
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.full_cr.eq(i.full_cr),
-                      self.cr_a.eq(i.cr_a)]
-
 
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)

diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py
index 089e601435d83937b9db6ba335ab3e08cbc872bf..063bb5b1dff0bd0f1938bd0dafa023cef2e33777 100644 (file)
--- a/src/soc/fu/ldst/pipe_data.py
+++ b/src/soc/fu/ldst/pipe_data.py
@@ -6,62 +6,27 @@ from soc.decoder.power_decoder2 import Data
 
 
 class LDSTInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('INT', 'rc', '0:63'),
-               ('XER', 'xer_so', '32')]
+    regspec = [('INT', 'ra', '0:63'), # RA
+               ('INT', 'rb', '0:63'), # RB/immediate
+               ('INT', 'rc', '0:63'), # RC
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.rc = Signal(64, reset_less=True) # RC
-        self.xer_so = Signal(reset_less=True) # XER bit 32: SO
+        super().__init__(pspec, False)
         # convenience
         self.rs = self.rc
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.rc
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.rc.eq(i.rc),
-                      self.xer_so.eq(i.xer_so)]
-
 
 class LDSTOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('INT', 'o1', '0:63'),
+    regspec = [('INT', 'o', '0:63'),   # RT
+               ('INT', 'o1', '0:63'),  # RA (effective address, update mode)
                ('CR', 'cr_a', '0:3'),
                ('XER', 'xer_so', '32')]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="stage_o")
-        self.o1 = Data(64, name="o1")
-        self.cr_a = Data(4, name="cr_a")
-        self.xer_so = Data(1, name="xer_so")
+        super().__init__(pspec, True)
         # convenience
         self.cr0, self.ea = self.cr_a, self.o1
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.o1
-        yield self.xer_ca
-        yield self.cr_a
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.o1.eq(i.o1),
-                      self.cr_a.eq(i.cr_a),
-                      self.xer_so.eq(i.xer_so)]
-
 
 class LDSTPipeSpec(CommonPipeSpec):
     regspec = (LDSTInputData.regspec, LDSTOutputData.regspec)

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 37e86d5aec1834aaf7ce5c78708b10619f424e8f..16cd3f5cae74ca683b3d1a26a43aa28cce09934e 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -7,53 +7,25 @@ from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
 class LogicalInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
+    regspec = [('INT', 'ra', '0:63'), # RA
+               ('INT', 'rb', '0:63'), # RB/immediate
                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB/immediate
+        super().__init__(pspec, False)
         # convenience
         self.a, self.b = self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb),
-                       ]
-
 
 class LogicalOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
+    regspec = [('INT', 'o', '0:63'),        # RT
                ('CR', 'cr_a', '0:3'),
-               ('XER', 'xer_ca', '34,45'),
+               ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
                ]
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="stage_o")  # RT
-        self.cr_a = Data(4, name="cr_a")
-        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
+        super().__init__(pspec, True)
         # convenience
         self.cr0 = self.cr_a
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.xer_ca
-        yield self.cr_a
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.cr_a.eq(i.cr_a),
-                      ]
-
 
 class LogicalPipeSpec(CommonPipeSpec):
     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)

diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py
index 3ceab14a1d69704b638f8a54ab323958b937727a..6d3b5aa533082ab4636d91e6489b6a2ec3d367d8 100644 (file)
--- a/src/soc/fu/pipe_data.py
+++ b/src/soc/fu/pipe_data.py
@@ -1,21 +1,38 @@
 from ieee754.fpcommon.getop import FPPipeContext
 from nmutil.dynamicpipe import SimpleHandshakeRedir
-
+from nmigen import Signal
+from soc.decoder.power_decoder2 import Data
+from soc.fu.regspec import get_regspec_bitwidth
 
 class IntegerData:
 
-    def __init__(self, pspec):
+    def __init__(self, pspec, output):
         self.ctx = FPPipeContext(pspec)
         self.muxid = self.ctx.muxid
+        self.data = []
+        self.is_output = output
+        for i, (regfile, regname, widspec) in enumerate(self.regspec):
+            wid = get_regspec_bitwidth([self.regspec], 0, i)
+            if output:
+                sig = Data(wid, name=regname)
+            else:
+                sig = Signal(wid, name=regname, reset_less=True)
+            setattr(self, regname, sig)
+            self.data.append(sig)
 
     def __iter__(self):
         yield from self.ctx
+        yield from self.data
 
     def eq(self, i):
-        return [self.ctx.eq(i.ctx)]
+        eqs = [self.ctx.eq(i.ctx)]
+        for j in range(len(self.data)):
+            eqs.append(self.data[j].eq(i.data[j]))
+        return eqs
 
     def ports(self):
-        return self.ctx.ports()
+        return self.ctx.ports() # TODO: include self.data
+
 
 # hmmm there has to be a better way than this
 def get_rec_width(rec):

diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 18b16f38c4dd7de455b6fb9f692656c1dd279294..75c629ab9eb3b2d477f5c7669a6ad3e7c3ee792a 100644 (file)
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -19,6 +19,7 @@ which MultiCompUnit port, how wide the connection is, and so on.
 from nmigen import Const
 from soc.regfile.regfiles import XERRegs, FastRegs
 
+
 def get_regspec_bitwidth(regspec, srcdest, idx):
     print ("get_regspec_bitwidth", regspec, srcdest, idx)
     bitspec = regspec[srcdest][idx]

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 044857526534a8382383b085feb5b8a62311beea..16f0655435a75eab03fbe5dfb543a143b51ad8fc 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -8,32 +8,15 @@ from nmutil.dynamicpipe import SimpleHandshakeRedir
 
 
 class ShiftRotInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('INT', 'rc', '0:63'),
-               ('XER', 'xer_ca', '34,45')]
+    regspec = [('INT', 'ra', '0:63'),      # RA
+               ('INT', 'rb', '0:63'),      # RB
+               ('INT', 'rc', '0:63'),      # RS
+               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.rb = Signal(64, reset_less=True) # RB
-        self.rc = Signal(64, reset_less=True) # RS
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
+        super().__init__(pspec, False)
         # convenience
         self.a, self.rs = self.ra, self.rc
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.rc
-        yield self.xer_ca
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.rc.eq(i.rc), self.ra.eq(i.ra),
-                      self.rb.eq(i.rb),
-                      self.xer_ca.eq(i.xer_ca) ]
-
 
 class ShiftRotPipeSpec(CommonPipeSpec):
     regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)

diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py
index eed1071116366292706a53e55255e42b63278ce2..007610af42901ee58732ce76dfe30e54af413df8 100644 (file)
--- a/src/soc/fu/spr/pipe_data.py
+++ b/src/soc/fu/spr/pipe_data.py
@@ -17,74 +17,27 @@ from soc.fu.spr.spr_input_record import CompSPROpSubset
 
 
 class SPRInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('SPR', 'spr1', '0:63'),
-               ('FAST', 'spr2', '0:63'),
-               ('XER', 'xer_so', '32'),
-               ('XER', 'xer_ov', '33,44'),
-               ('XER', 'xer_ca', '34,45')]
+    regspec = [('INT', 'ra', '0:63'),        # RA
+               ('SPR', 'spr1', '0:63'),      # SPR (slow)
+               ('FAST', 'spr2', '0:63'),     # SPR (fast: MSR, LR, CTR etc)
+               ('XER', 'xer_so', '32'),      # XER bit 32: SO
+               ('XER', 'xer_ov', '33,44'),   # XER bit 34/45: CA/CA32
+               ('XER', 'xer_ca', '34,45')]   # bit0: ov, bit1: ov32
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True) # RA
-        self.spr1 = Signal(64, reset_less=True) # SPR (slow)
-        self.spr2 = Signal(64, reset_less=True) # SPR (fast: MSR, LR, CTR etc)
-        self.xer_so = Signal(reset_less=True) # XER bit 32: SO
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
-        self.xer_ov = Signal(2, reset_less=True) # bit0: ov, bit1: ov32
+        super().__init__(pspec, False)
         # convenience
         self.a = self.ra
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.spr1
-        yield self.spr2
-        yield self.xer_ca
-        yield self.xer_ov
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.reg.eq(i.reg),
-                      self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.xer_ov.eq(i.xer_ov),
-                      self.xer_so.eq(i.xer_so)]
-
 
 class SPROutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('SPR', 'spr1', '0:63'),
-               ('FAST', 'spr2', '0:63'),
-               ('XER', 'xer_so', '32'),
-               ('XER', 'xer_ov', '33,44'),
-               ('XER', 'xer_ca', '34,45')]
+    regspec = [('INT', 'o', '0:63'),        # RT
+               ('SPR', 'spr1', '0:63'),     # SPR (slow)
+               ('FAST', 'spr2', '0:63'),    # SPR (fast: MSR, LR, CTR etc)
+               ('XER', 'xer_so', '32'),     # XER bit 32: SO
+               ('XER', 'xer_ov', '33,44'),  # XER bit 34/45: CA/CA32
+               ('XER', 'xer_ca', '34,45')]  # bit0: ov, bit1: ov32
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="rt") # RT
-        self.spr1 = Data(64, name="spr1") # SPR (slow)
-        self.spr2 = Data(64, name="spr2") # SPR (fast: MSR, LR, CTR etc)
-        self.xer_so = Data(1, name="xer_so") # XER bit 32: SO
-        self.xer_ca = Data(2, name="xer_ca") # XER bit 34/45: CA/CA32
-        self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
-
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.spr1
-        yield self.spr2
-        yield self.xer_ca
-        yield self.xer_ov
-        yield self.xer_so
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.o.eq(i.o), self.reg.eq(i.reg),
-                      self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.xer_ov.eq(i.xer_ov),
-                      self.xer_so.eq(i.xer_so)]
-
+        super().__init__(pspec, True)
 
 
 class SPRPipeSpec:

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 8b4e343a525cbfd041155dfcdc69843e25f9201a..e0cc881ecdcf076359cc094afae91f08f5aac52c 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -7,63 +7,28 @@ from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
 
 
 class TrapInputData(IntegerData):
-    regspec = [('INT', 'ra', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('FAST', 'spr1', '0:63'),
-               ('FAST', 'cia', '0:63'),
-               ('FAST', 'msr', '0:63')]
+    regspec = [('INT', 'ra', '0:63'),  # RA
+               ('INT', 'rb', '0:63'),  # RB/immediate
+               ('FAST', 'spr1', '0:63'), # SRR0
+               ('FAST', 'cia', '0:63'),  # Program counter (current)
+               ('FAST', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.ra = Signal(64, reset_less=True)  # RA
-        self.rb = Signal(64, reset_less=True)  # RB/immediate
-        self.spr1 = Data(64, name="spr1") # SRR0
-        self.cia = Signal(64, reset_less=True)  # Program counter
-        self.msr = Signal(64, reset_less=True)  # MSR
+        super().__init__(pspec, False)
         # convenience
         self.srr0, self.a, self.b = self.spr1, self.ra, self.rb
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.ra
-        yield self.rb
-        yield self.spr1
-        yield self.cia
-        yield self.msr
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb), self.spr1.eq(i.spr1),
-                      self.cia.eq(i.cia), self.msr.eq(i.msr)]
-
 
 class TrapOutputData(IntegerData):
-    regspec = [('INT', 'o', '0:63'),
-               ('FAST', 'spr1', '0:63'),
-               ('FAST', 'spr2', '0:63'),
-               ('FAST', 'nia', '0:63'),
-               ('FAST', 'msr', '0:63')]
+    regspec = [('INT', 'o', '0:63'),     # RA
+               ('FAST', 'spr1', '0:63'), # SRR0 SPR
+               ('FAST', 'spr2', '0:63'), # SRR1 SPR
+               ('FAST', 'nia', '0:63'),  # NIA (Next PC)
+               ('FAST', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
-        super().__init__(pspec)
-        self.o = Data(64, name="o")       # RA
-        self.spr1 = Data(64, name="spr1") # SRR0 SPR
-        self.spr2 = Data(64, name="spr2") # SRR1 SPR
-        self.nia = Data(64, name="nia") # NIA (Next PC)
-        self.msr = Data(64, name="msr") # MSR
+        super().__init__(pspec, True)
         # convenience
         self.srr0, self.srr1 = self.spr1, self.spr2
 
-    def __iter__(self):
-        yield from super().__iter__()
-        yield self.o
-        yield self.nia
-        yield self.msr
-        yield self.spr1
-        yield self.spr2
-
-    def eq(self, i):
-        lst = super().eq(i)
-        return lst + [ self.o.eq(i.o), self.nia.eq(i.nia), self.msr.eq(i.msr),
-                      self.spr1.eq(i.spr1), self.spr2.eq(i.spr2)]
 
 
 # TODO: replace CompALUOpSubset with CompTrapOpSubset