Add ability to specify initial state for SPRs
[soc.git] / src / soc / alu /
2020-05-11 Michael NolanAdd ability to specify initial state for SPRs
2020-05-11 Michael NolanFix proof_input_stage.py
2020-05-11 Michael NolanFix rlwimi by reordering the inputs *again*
2020-05-11 Michael NolanRe-enable rlwinm test
2020-05-11 Michael NolanCheck write register number too
2020-05-11 Michael NolanReorder the register reads so the field in read_reg2...
2020-05-11 Michael NolanHave test_pipe_caller actually read from the registers...
2020-05-11 Michael NolanActually implement rlwimi
2020-05-11 Luke Kenneth Casso... comment input signals
2020-05-11 Luke Kenneth Casso... cleanup rotator.py
2020-05-11 Luke Kenneth Casso... add docstring, missing return module
2020-05-11 Luke Kenneth Casso... start cleanup of rotator.py, Cat order is inverted
2020-05-11 Luke Kenneth Casso... convert microwatt rotator to nmigen (first draft)
2020-05-10 Michael NolanAdd test for rlwnm
2020-05-10 Michael NolanImplement rlwimi as well
2020-05-10 Michael NolanImplement rlwinm in alu
2020-05-10 Michael NolanReduce BMC depth on proof_main_stage.py
2020-05-10 Luke Kenneth Casso... use temporary python vars rather than copy signals...
2020-05-09 Michael NolanAdd shift left and shift right to main stage proof
2020-05-09 Luke Kenneth Casso... sigh ton of syntax errors
2020-05-09 Luke Kenneth Casso... bit of reorg, trick on add - put carry in into the LSB
2020-05-09 Luke Kenneth Casso... comment output stage
2020-05-09 Luke Kenneth Casso... comment maskgen
2020-05-09 Michael NolanHandle algebraic shifts too
2020-05-09 Michael NolanImplement logical shift right
2020-05-09 Michael NolanAdd support for sld
2020-05-09 Michael NolanChange shift left to be implemented with rotate and...
2020-05-09 Michael NolanAdd mask generator for shift class instructions
2020-05-09 Michael NolanAdd shift left opcode to main_stage
2020-05-09 Luke Kenneth Casso... comment where ALUIntermediateData to go
2020-05-09 Luke Kenneth Casso... TODO on AluIntermediateData
2020-05-09 Luke Kenneth Casso... missing sticky-overflow pass-through from middle stage
2020-05-09 Luke Kenneth Casso... pass through sticky-overflow
2020-05-09 Luke Kenneth Casso... remove unneeded class
2020-05-09 Luke Kenneth Casso... clarifying comments
2020-05-09 Michael NolanMinor cleanup
2020-05-08 Luke Kenneth Casso... add comments
2020-05-08 Luke Kenneth Casso... add ALUFirstInputData
2020-05-08 Michael NolanOops, forgot pipeline.py
2020-05-08 Michael NolanAdd tests for immediates, add subf to tests
2020-05-08 Michael NolanAdd comments about the purpose of each alu stage
2020-05-08 Michael NolanAdd test for alu against simulator
2020-05-08 Michael NolanAdd assertions for output stage cr0
2020-05-08 Michael NolanAdd output stage
2020-05-08 Michael NolanAdd and or and xor to main_stage
2020-05-08 Michael NolanAdd carry in and out
2020-05-08 Michael NolanHave input_stage set the b operand to imm_data if it...
2020-05-08 Michael NolanAdd extra bits (carry, overflow, etc) to input and...
2020-05-08 Michael NolanBegin adding main ALU stage
2020-05-08 Michael NolanConvert alu to use the op in ctx
2020-05-08 Michael NolanAdd FPPipeContext to alu pipe_data
2020-05-08 Michael NolanAdd handling of A inversion and B input
2020-05-08 Michael NolanBegin adding input stage of alu
2020-05-08 Michael NolanAdd pipe data for ALU pipeline
2020-05-08 Michael NolanSeparate out ALU Input record from alu_hier.py