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Add ability to specify initial state for SPRs
[soc.git]
/
src
/
soc
/
alu
/
2020-05-11
Michael Nolan
Add ability to specify initial state for SPRs
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2020-05-11
Michael Nolan
Fix proof_input_stage.py
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2020-05-11
Michael Nolan
Fix rlwimi by reordering the inputs *again*
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2020-05-11
Michael Nolan
Re-enable rlwinm test
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2020-05-11
Michael Nolan
Check write register number too
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2020-05-11
Michael Nolan
Reorder the register reads so the field in read_reg2...
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2020-05-11
Michael Nolan
Have test_pipe_caller actually read from the registers...
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2020-05-11
Michael Nolan
Actually implement rlwimi
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2020-05-11
Luke Kenneth Casso...
comment input signals
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2020-05-11
Luke Kenneth Casso...
cleanup rotator.py
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2020-05-11
Luke Kenneth Casso...
add docstring, missing return module
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2020-05-11
Luke Kenneth Casso...
start cleanup of rotator.py, Cat order is inverted
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2020-05-11
Luke Kenneth Casso...
convert microwatt rotator to nmigen (first draft)
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2020-05-10
Michael Nolan
Add test for rlwnm
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2020-05-10
Michael Nolan
Implement rlwimi as well
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2020-05-10
Michael Nolan
Implement rlwinm in alu
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2020-05-10
Michael Nolan
Reduce BMC depth on proof_main_stage.py
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2020-05-10
Luke Kenneth Casso...
use temporary python vars rather than copy signals...
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2020-05-09
Michael Nolan
Add shift left and shift right to main stage proof
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2020-05-09
Luke Kenneth Casso...
sigh ton of syntax errors
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2020-05-09
Luke Kenneth Casso...
bit of reorg, trick on add - put carry in into the LSB
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2020-05-09
Luke Kenneth Casso...
comment output stage
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2020-05-09
Luke Kenneth Casso...
comment maskgen
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2020-05-09
Michael Nolan
Handle algebraic shifts too
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2020-05-09
Michael Nolan
Implement logical shift right
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2020-05-09
Michael Nolan
Add support for sld
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2020-05-09
Michael Nolan
Change shift left to be implemented with rotate and...
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2020-05-09
Michael Nolan
Add mask generator for shift class instructions
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2020-05-09
Michael Nolan
Add shift left opcode to main_stage
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2020-05-09
Luke Kenneth Casso...
comment where ALUIntermediateData to go
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2020-05-09
Luke Kenneth Casso...
TODO on AluIntermediateData
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2020-05-09
Luke Kenneth Casso...
missing sticky-overflow pass-through from middle stage
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2020-05-09
Luke Kenneth Casso...
pass through sticky-overflow
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2020-05-09
Luke Kenneth Casso...
remove unneeded class
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2020-05-09
Luke Kenneth Casso...
clarifying comments
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2020-05-09
Michael Nolan
Minor cleanup
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2020-05-08
Luke Kenneth Casso...
add comments
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2020-05-08
Luke Kenneth Casso...
add ALUFirstInputData
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2020-05-08
Michael Nolan
Oops, forgot pipeline.py
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2020-05-08
Michael Nolan
Add tests for immediates, add subf to tests
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2020-05-08
Michael Nolan
Add comments about the purpose of each alu stage
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2020-05-08
Michael Nolan
Add test for alu against simulator
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2020-05-08
Michael Nolan
Add assertions for output stage cr0
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2020-05-08
Michael Nolan
Add output stage
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2020-05-08
Michael Nolan
Add and or and xor to main_stage
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2020-05-08
Michael Nolan
Add carry in and out
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2020-05-08
Michael Nolan
Have input_stage set the b operand to imm_data if it...
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2020-05-08
Michael Nolan
Add extra bits (carry, overflow, etc) to input and...
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2020-05-08
Michael Nolan
Begin adding main ALU stage
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2020-05-08
Michael Nolan
Convert alu to use the op in ctx
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2020-05-08
Michael Nolan
Add FPPipeContext to alu pipe_data
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2020-05-08
Michael Nolan
Add handling of A inversion and B input
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2020-05-08
Michael Nolan
Begin adding input stage of alu
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2020-05-08
Michael Nolan
Add pipe data for ALU pipeline
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2020-05-08
Michael Nolan
Separate out ALU Input record from alu_hier.py
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