add trunc_div and trunch_rem to decoder helpers
[soc.git] / src / soc / decoder /
2020-06-19 Luke Kenneth Casso... add trunc_div and trunch_rem to decoder helpers
2020-06-19 Luke Kenneth Casso... auto-assign needs to use concat / selectconcat
2020-06-19 Luke Kenneth Casso... whoops detected page name wrong, for special case fixed...
2020-06-19 Luke Kenneth Casso... bit of a mess. getting carry recognised and output...
2020-06-19 Luke Kenneth Casso... add auto-assign mode detecting uninitialised variable...
2020-06-19 Luke Kenneth Casso... div needs to be floordiv
2020-06-19 Luke Kenneth Casso... add true and floor div to SelectableInt
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... investigating mtocrf/mtcrf issue
2020-06-17 Luke Kenneth Casso... add bug reference to mtocrf/mtcrf name decoding
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... getting sim instruction decoder to reproduce asm instru...
2020-06-17 Luke Kenneth Casso... add comment/assembly decode in power enums
2020-06-17 Luke Kenneth Casso... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... got fed up of adding arguments to ISACaller / ISA,...
2020-06-17 Luke Kenneth Casso... split execute and setup of ISACaller instruction execution
2020-06-17 Luke Kenneth Casso... comment ISACaller setup
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... add a fake program counter to ISACaller
2020-06-17 Luke Kenneth Casso... add "respect_pc" boolean to ISACaller
2020-06-17 Luke Kenneth Casso... add optional instruction memory
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... note possible BE/LE mode needed for memory reads/writes
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-10 Luke Kenneth Casso... move Decode2ToExecute1Type to separate module
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... code-morph regspecmap functions, split into separate...
2020-06-09 Luke Kenneth Casso... map LDST len directly, rather than go through a switch...
2020-06-09 Luke Kenneth Casso... bit more on TRAP handling (preparing priv instruction)
2020-06-08 Luke Kenneth Casso... add traptype and trapaddr to PowerDecoder2. idea is...
2020-06-08 Luke Kenneth Casso... add "instr_is_privileged" to power_decoder2 (untested)
2020-06-08 Luke Kenneth Casso... use 2nd shortened convenience variable in PowerDecoder2
2020-06-08 Luke Kenneth Casso... use shortened convenience variable in PowerDecoder2
2020-06-08 Luke Kenneth Casso... add comment docstring about POWER9 simulator
2020-06-08 Luke Kenneth Casso... whoops, overflow-decode (handle_overflow) needed to...
2020-06-08 Luke Kenneth Casso... add CA/CA32 to write regs fields in parser
2020-06-08 Luke Kenneth Casso... check that carry has already been done or not by the...
2020-06-08 Luke Kenneth Casso... copy 64-bit OV, try creating 32-bit OV32 in
2020-06-07 Luke Kenneth Casso... update comments
2020-06-07 Luke Kenneth Casso... resolved CR mfcr lookup bug (was in power_decoder. ??)
2020-06-07 Luke Kenneth Casso... how odd. just adding CA32 to self.namespace seems...
2020-06-07 Luke Kenneth Casso... ha! set XER CA/CA32 in simulator from output.value...
2020-06-07 Luke Kenneth Casso... optionally writing out CA/CA32 to XER
2020-06-07 Luke Kenneth Casso... add handling of CA/CA32 in simulator, generated from...
2020-06-07 Luke Kenneth Casso... add CA/CA32 to list of special regs
2020-06-07 Luke Kenneth Casso... Revert "if referred to through GPR (GPR[RA]), add to...
2020-06-07 Luke Kenneth Casso... Revert "remove fixedlogical.patch - added gprs to Power...
2020-06-07 Luke Kenneth Casso... Revert "add gprs to PowerParser write_regs in p_atom_name"
2020-06-07 Luke Kenneth Casso... if referred to through GPR (GPR[RA]), add to read_regs...
2020-06-07 Luke Kenneth Casso... add gprs to PowerParser write_regs in p_atom_name
2020-06-07 Luke Kenneth Casso... remove fixedlogical.patch - added gprs to PowerParser...
2020-06-07 Luke Kenneth Casso... docstring on caller.py inject() decorator
2020-06-07 Luke Kenneth Casso... add TRAP function, stub
2020-06-07 Luke Kenneth Casso... add MSR to simulator context
2020-06-06 Luke Kenneth Casso... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... shift-mask in Simulator Mem class not quite right
2020-06-06 Luke Kenneth Casso... allow Mem in Simulator to be initialised
2020-06-05 Luke Kenneth Casso... whoops returning cr2 for cr3 regspec map
2020-06-05 Luke Kenneth Casso... fix syntax errors and use correct FastRegs (SRR0/1...
2020-06-05 Luke Kenneth Casso... add TODO for MFSPR/MTSPR
2020-06-05 Luke Kenneth Casso... add OP_RFID SRR0/SRR1 in PowerDecode2
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth Casso... reduce amount of code in SelectableInt
2020-06-04 Luke Kenneth Casso... messing with valid/busy signals in core test
2020-06-04 Luke Kenneth Casso... whitespace
2020-06-04 Luke Kenneth Casso... test actual reg values being produced in core test
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Luke Kenneth Casso... correct comments on regspec decode map
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... worked out how to dynamically enable carry-in to ALU...
2020-06-03 Luke Kenneth Casso... correct overflow-enable flags for rdmask specs in ALU
2020-06-03 Luke Kenneth Casso... attempt to make carry-in and overflow-enable optional...
2020-06-03 Luke Kenneth Casso... move over to using power_regspec_map.py from PowerDecod...
2020-06-03 Luke Kenneth Casso... mention TODO on SPR regfile
2020-06-02 Luke Kenneth Casso... add lk field to DecodeOut2
2020-06-02 Luke Kenneth Casso... Revert "ok ok - for OP_BCREG put CTR in spr2 as well"
2020-06-02 Luke Kenneth Casso... ok ok - for OP_BCREG put CTR in spr2 as well
2020-06-02 Luke Kenneth Casso... set up CTR and LR only on BCREG when needed
2020-06-02 Luke Kenneth Casso... decode fast spr for OP_BCREG CTR, TAR and LR
2020-06-02 Luke Kenneth Casso... debugging branch fast registers
2020-06-02 Luke Kenneth Casso... add regspecmap function to PowerDecode2
2020-06-02 Luke Kenneth Casso... move regspec function to separate module
2020-06-02 Luke Kenneth Casso... add in fast regs support in decoder and into regspec_decode
2020-06-02 Luke Kenneth Casso... add 2nd write-reg for LD/ST Update mode
2020-06-02 Luke Kenneth Casso... add read-write register numbering detection
2020-06-01 Luke Kenneth Casso... remove unneeded fields from Decode2Execute1Type
2020-06-01 Luke Kenneth Casso... allow ALU / Logical ops to select RS as 1st operand
2020-06-01 Luke Kenneth Casso... allow M*-Form shiftrot to swap RS/RB back to consistent...
2020-06-01 Luke Kenneth Casso... decode SPRs for branch
2020-05-30 Luke Kenneth Casso... select CR0 write out only when RC=1
2020-05-28 Michael NolanAdd OP_SETB
2020-05-27 Luke Kenneth Casso... make power function unit enum bitmasked
2020-05-25 Luke Kenneth Casso... add INT, SPR and CR regfiles
2020-05-24 Luke Kenneth Casso... add MFMSR and MTMSRD enums to Function
2020-05-23 Luke Kenneth Casso... select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
2020-05-22 Luke Kenneth Casso... over 80 chars
2020-05-21 Luke Kenneth Casso... add CR out decoder debug
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