Allow more test cases to be run with CXXSim
[soc.git] / src / soc / experiment / dcache.py
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim
2020-10-05 Luke Kenneth Casso... add debug / investigation print statements
2020-10-01 Luke Kenneth Casso... arg CacheRam read output needs delay by 1 cycle
2020-10-01 Luke Kenneth Casso... do not pass cache row array around, just the current row
2020-09-14 Luke Kenneth Casso... increase TLB_NUM_WAYS to 4
2020-09-14 Luke Kenneth Casso... add array signal names
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... TLB PLRUs are of TLB_WAY_BITS width
2020-09-14 Luke Kenneth Casso... fix mmu perms/lookup in dcache
2020-09-13 Luke Kenneth Casso... dcache truncate wishbone address, store real_addr in...
2020-09-13 Luke Kenneth Casso... MMU test
2020-09-13 Luke Kenneth Casso... sort out ariane PLRU, rename/clarify
2020-09-13 Luke Kenneth Casso... rename cache_valid_bits to cache_validsg
2020-09-13 Luke Kenneth Casso... cache_valid_idx too large in dcache
2020-09-13 Luke Kenneth Casso... whoops, cache valid array too small in dcache
2020-09-12 Luke Kenneth Casso... more dcache debugging
2020-09-12 Luke Kenneth Casso... missing reservation address comparison
2020-09-12 Luke Kenneth Casso... dcache tidyup
2020-09-12 Luke Kenneth Casso... more dcache debugging
2020-09-12 Luke Kenneth Casso... add random dcache mem test
2020-09-12 Luke Kenneth Casso... cache valid corrupted: fixed
2020-09-12 Luke Kenneth Casso... adding names to array signals
2020-09-12 Luke Kenneth Casso... whoops, indentation error
2020-09-12 Luke Kenneth Casso... enable Display debugs
2020-09-12 Luke Kenneth Casso... set bytesel in dcache store
2020-09-11 Luke Kenneth Casso... separat stbs_done into ld/st
2020-09-11 Luke Kenneth Casso... dcache load/store test
2020-09-11 Luke Kenneth Casso... debugging dcache
2020-09-11 Luke Kenneth Casso... connect up WB SRAM to dcache test
2020-09-11 Luke Kenneth Casso... start on dcache test
2020-09-11 Luke Kenneth Casso... missing comb +=
2020-09-11 Luke Kenneth Casso... missing maybe_tlb_plrus
2020-09-11 Luke Kenneth Casso... WAY_BITS not TLB_WAY_BITS
2020-09-11 Luke Kenneth Casso... try to get better DTLBUpdate
2020-09-11 Luke Kenneth Casso... simplify dcache pending
2020-09-11 Luke Kenneth Casso... move dcache pending test to separate module
2020-09-11 Luke Kenneth Casso... more error correction in dcache
2020-09-11 Luke Kenneth Casso... use module for TLBUpdate
2020-09-11 Luke Kenneth Casso... add brackets round if & in dcache
2020-09-11 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-09-10 Luke Kenneth Casso... simplify read/write pte
2020-09-10 Luke Kenneth Casso... eek, big sort-out of syntax errors in dcache.py, now...
2020-09-10 Luke Kenneth Casso... starting on dcache syntax errors
2020-09-10 Luke Kenneth Casso... add PLRU microwatt conversion
2020-09-10 Luke Kenneth Casso... add function calls to construct dcache
2020-09-10 Luke Kenneth Casso... correct some errors introduced in dcache.py
2020-09-09 Luke Kenneth Casso... more laborious line-by-line checking of dcache.py conve...
2020-09-07 Luke Kenneth Casso... large stack of moving stuff around in dcache
2020-09-07 Luke Kenneth Casso... adjust indentation of dcache_slow
2020-09-07 Luke Kenneth Casso... more dcache translation
2020-09-07 Luke Kenneth Casso... more dcache translation
2020-09-03 Luke Kenneth Casso... do more on dcache conversion
2020-08-30 Luke Kenneth Casso... working on dcache.py
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza...
2020-08-28 Cole Poirierdcache.py add first attempt at translation of dcache_tb...
2020-08-27 Cole Poirierdcache.py add skeleton sim and test adapted from mmu...
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Cole Poirierdcache.py implement the remaining vhdl generate stateme...
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Cole Poirierdcache.py replace subtypes/types/constant aliases with...
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Cole Poirierdcache.py rearrange, transform classes into functions...
2020-08-25 Cole Poirierdcache.py fix whitespace, fomatting, syntax
2020-08-25 Cole Poirierdcache.py fix formatting
2020-08-25 Cole Poirierdcache.py move Reservation RecordObject to top of file
2020-08-25 Cole Poirierdcache.py move RegStage1 RecordObject to top of file
2020-08-25 Cole Poirierdcache.py move MemAccessRequest RecordObject to top...
2020-08-25 Cole Poirierdcache.py move Stage0 RecordObject to top of file
2020-08-24 Luke Kenneth Casso... tidyup / shuffle after review
2020-08-24 Luke Kenneth Casso... remove default parameter
2020-08-24 Luke Kenneth Casso... "WAY" does not exist - range(NUM_WAYS) was intended
2020-08-24 Luke Kenneth Casso... use WAY_BITS in appropriate locations
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-24 Cole Poirierdcache.py commit first full tranlation pass, about...
2020-08-21 Luke Kenneth Casso... remove extraneous comments
2020-08-21 Cole Poirierdcache.py fix asserts, use backslash and two strings...
2020-08-21 Cole Poirierdcache.py replace functions that return signals with...
2020-08-21 Luke Kenneth Casso... comment formatting
2020-08-21 Luke Kenneth Casso... remove default values
2020-08-21 Luke Kenneth Casso... just range(the_constant)
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-21 Cole Poirierdcache.py commit today and yesterday's progress (sorry...
2020-08-19 Luke Kenneth Casso... comments in dcache
2020-08-18 Luke Kenneth Casso... add comment in dcache.py
2020-08-17 Cole Poirierdcache.py commit today's progress on translating dcache...
2020-08-13 Cole Poirierdcache.py add initial imports
2020-08-13 Cole PoirierInitial commit of translation of microwatt dcache.vhdl...