tidyup comments and remove LoadStore COMPLETE state
[soc.git] / src / soc / fu / spr /
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-04-23 Luke Kenneth Casso... move SPR tests to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2020-12-13 Cesar StraussIgnore formal verification output in the source directory
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-06 Luke Kenneth Casso... add unit test for slow SPRs (SPRG0/1)
2020-09-06 Luke Kenneth Casso... minor code-munge on SPR-to-FAST mapping
2020-09-06 Luke Kenneth Casso... use with subTest in spr unit test
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth Casso... add DEC/TB SPRs to spr pipeline
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr
2020-08-18 Luke Kenneth Casso... fix spr state test
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayadd code for skipping test cases
2020-07-26 Luke Kenneth Casso... convert SPR test to accumulator style
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... convert branch pipeline to use msr/cia as immediates
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... comments
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Luke Kenneth Casso... use convenience vars in spr proof
2020-07-17 Samuel A. Falvo IIFlesh out SPR-related FV properties.
2020-07-16 Luke Kenneth Casso... whoops tried doing mtspr priv, it failed but failed... div_pipeline
2020-07-16 Luke Kenneth Casso... more tidyup on use of CompOpSubsetBase
2020-07-15 Luke Kenneth Casso... no need to check individual port members, just check...
2020-07-14 Luke Kenneth Casso... cookie-cut setup from alu proof_main_stage.py
2020-07-14 Luke Kenneth Casso... split out CompOpSubsetBase (meaning to do for a while)
2020-07-14 Luke Kenneth Casso... update docstrings
2020-07-14 Samuel A. Falvo IISPR: FV that should fail currently passes
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Luke Kenneth Casso... add to/from spr test (mtspr, mfspr)
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... get/set slow spr in spr test_pipe_caller
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-07-04 Luke Kenneth Casso... add spr test, add decode of spr in/out
2020-07-04 Luke Kenneth Casso... add spr main stage
2020-07-04 Luke Kenneth Casso... add spr input record
2020-07-04 Luke Kenneth Casso... add SPR pipeline
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... convenience rename for spr pipe_data.py, consistent...
2020-05-24 Luke Kenneth Casso... add comments for SPR pipe_data
2020-05-24 Luke Kenneth Casso... add SPR pipe_data.py