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Initialize the core SVSTATE from the corresponding test case
[soc.git] / src /
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding... tree | commitdiff
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the... tree | commitdiff
2021-02-17 Cesar StraussAdd a function to select bits from a signal into a... tree | commitdiff
2021-02-17 Luke Kenneth Casso... fix reg read/write in ISACaller, PowerDecoder2 handles... tree | commitdiff
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register... tree | commitdiff
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues tree | commitdiff
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start tree | commitdiff
2021-02-16 Cesar StraussFix MSB0 issues for SVP64 tree | commitdiff
2021-02-16 Tobias Platenmmureq handling tree | commitdiff
2021-02-16 Tobias Platendcache error handling tree | commitdiff
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-02-16 Luke Kenneth Casso... ordering wrong on svstate in ISACaller tree | commitdiff
2021-02-16 Luke Kenneth Casso... adapt botchify so it can be used for 31- or 15- etc... tree | commitdiff
2021-02-16 Luke Kenneth Casso... add indicator to PowerDecoder2 when no outputs are... tree | commitdiff
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it... tree | commitdiff
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL tree | commitdiff
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file tree | commitdiff
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-02-14 Cesar StraussShow traces for the register numbers of the current... tree | commitdiff
2021-02-14 Cesar StraussFix width of the "extra" input on the Extra decoder tree | commitdiff
2021-02-14 Cesar StraussFix conversion to MSB0 tree | commitdiff
2021-02-14 Cesar StraussRemove obsolete comment tree | commitdiff
2021-02-14 Luke Kenneth Casso... add comments to TestIssuer tree | commitdiff
2021-02-14 Luke Kenneth Casso... add srcstep onto Vectorised GPRs in PowerDecoder2 tree | commitdiff
2021-02-14 Luke Kenneth Casso... add TestRunner comments tree | commitdiff
2021-02-14 Luke Kenneth Casso... add Regfiles comments tree | commitdiff
2021-02-14 Luke Kenneth Casso... add SVSTATE reading to TestIssuer tree | commitdiff
2021-02-14 Luke Kenneth Casso... add SVSTATE to CoreState tree | commitdiff
2021-02-14 Luke Kenneth Casso... add extra FSM explanatory comments to TestIssuer tree | commitdiff
2021-02-13 Luke Kenneth Casso... use function for getting instruction from 32/64 bit... tree | commitdiff
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix tree | commitdiff
2021-02-13 Tobias PlatenOP_TLBIE must in be instr_is_priv tree | commitdiff
2021-02-13 Tobias Platenkeep commits to under 80 chars tree | commitdiff
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction tree | commitdiff
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case tree | commitdiff
2021-02-13 Cesar StraussFix imports and whitespace tree | commitdiff
2021-02-13 Luke Kenneth Casso... update svp64 unit test comments tree | commitdiff
2021-02-13 Tobias Platenforward microwatt mmu specific SPR: PID and PRTBL tree | commitdiff
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test tree | commitdiff
2021-02-13 Luke Kenneth Casso... split out TestRunner into separate module tree | commitdiff
2021-02-13 Cesar StraussFix SVP64 translator to yield the unaltered instruction tree | commitdiff
2021-02-12 Luke Kenneth Casso... add one SVP64 ALU test case to get started tree | commitdiff
2021-02-12 Luke Kenneth Casso... add SVSTATE to TestCase infrastructure for use in TestI... tree | commitdiff
2021-02-12 Luke Kenneth Casso... add skip of instruction if SVSTATE.VL=0 in ISACaller tree | commitdiff
2021-02-12 Luke Kenneth Casso... validate all registers to make sure no damage occurs... tree | commitdiff
2021-02-12 Luke Kenneth Casso... add srcstep and correct PC-advancing during Sub-PC... tree | commitdiff
2021-02-12 Luke Kenneth Casso... comments tree | commitdiff
2021-02-12 Luke Kenneth Casso... add in SVSTATE.srcstep update, loop from 0 to VL-1 tree | commitdiff
2021-02-12 Luke Kenneth Casso... allow PC to update by 8 in SVP64 mode tree | commitdiff
2021-02-12 Luke Kenneth Casso... fix setting of SVSTATE.VL and MVL tree | commitdiff
2021-02-12 Luke Kenneth Casso... add in SVSTATE to ISACaller, not used, just passed in tree | commitdiff
2021-02-11 Luke Kenneth Casso... comments in TestIssuer for SVP64PrefixDecoder tree | commitdiff
2021-02-10 Luke Kenneth Casso... add svp64 reg decode detection to ISACaller output tree | commitdiff
2021-02-10 Luke Kenneth Casso... starting to add SVP64 register EXTRA-read and isvec... tree | commitdiff
2021-02-10 Luke Kenneth Casso... comment update tree | commitdiff
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore tree | commitdiff
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal... tree | commitdiff
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_... tree | commitdiff
2021-02-07 colepoiriericache.py fix formatting tree | commitdiff
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent... tree | commitdiff
2021-02-06 Cesar StraussFix whitespace tree | commitdiff
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM tree | commitdiff
2021-02-05 Tobias Platenfix hanging simulation tree | commitdiff
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave tree | commitdiff
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs tree | commitdiff
2021-02-04 Tobias Platenpass SPR MicroOp to MMU function unit tree | commitdiff
2021-02-03 Luke Kenneth Casso... nope - need it to be zero if not identified as svp64 tree | commitdiff
2021-02-03 Luke Kenneth Casso... actually no need to mux in the svp64_rm, just the id... tree | commitdiff
2021-02-03 Luke Kenneth Casso... add SVP64PowerDecoder, extracts svp64 remap if correctl... tree | commitdiff
2021-02-01 Luke Kenneth Casso... ISACaller, in svp64 mode, read the next 32 bits when... tree | commitdiff
2021-02-01 Tobias Platenextending the GTKWave document in test_issuer when... tree | commitdiff
2021-02-01 Luke Kenneth Casso... sort out SelectableInt bit-ordering for identifying... tree | commitdiff
2021-02-01 Luke Kenneth Casso... construct the assembly-code prefix and base v3.0B in... tree | commitdiff
2021-02-01 Cesar StraussAdd GTKWave document to test_issuer tree | commitdiff
2021-01-31 Cesar StraussFix loop test and enable it tree | commitdiff
2021-01-31 Luke Kenneth Casso... start an ISACaller SVP64 unit test tree | commitdiff
2021-01-31 Luke Kenneth Casso... test SVP64 major opcode, start checking if it is EXT001... tree | commitdiff
2021-01-31 Luke Kenneth Casso... adjusting ISACaller unit test to use ISACaller.setup_one() tree | commitdiff
2021-01-31 Luke Kenneth Casso... fix ISACaller unit test tree | commitdiff
2021-01-31 Tobias Platenfix two syntax errors in src/soc/decoder/isa/caller.py tree | commitdiff
2021-01-31 Luke Kenneth Casso... SVP64 Remap Fields structures for ISACaller tree | commitdiff
2021-01-31 Luke Kenneth Casso... remove sv_rm from PowerDecoder register decoders tree | commitdiff
2021-01-31 Luke Kenneth Casso... add SVSTATE SPR sub-field accessor class to ISACaller tree | commitdiff
2021-01-31 Luke Kenneth Casso... move SVP64 Extra reg decoding into main PowerDecoder... tree | commitdiff
2021-01-31 Luke Kenneth Casso... update submodule tree | commitdiff
2021-01-30 Luke Kenneth Casso... move CR in/out SVP64 EXTRA decoders into PowerDecoder tree | commitdiff
2021-01-30 Luke Kenneth Casso... add SVP64 CR out extending to 7-bit in PowerDecoder2 tree | commitdiff
2021-01-30 Luke Kenneth Casso... add SVP64 CR EXTRA field-extension, from 3-bit to 7... tree | commitdiff
2021-01-30 Luke Kenneth Casso... extend CR registers in Decode2ToExecute1Type to 7 bit tree | commitdiff
2021-01-30 Luke Kenneth Casso... add SVP64CRExtra class to PowerDecoder2, turns 3-bit... tree | commitdiff
2021-01-30 Luke Kenneth Casso... split out SVEXTRA field selection/decoding into separat... tree | commitdiff
2021-01-30 Luke Kenneth Casso... whoops update PowerDecoder2 svp64 comments, reg sizes... tree | commitdiff
2021-01-30 Luke Kenneth Casso... add SVP64 EXTRA decoding to RB, RC and RT (out) in... tree | commitdiff
2021-01-30 Luke Kenneth Casso... add first SVP64 7-bit register context decoder to Power... tree | commitdiff
2021-01-29 Luke Kenneth Casso... add SVP64RM record to PowerDecoder2 tree | commitdiff
2021-01-29 Luke Kenneth Casso... increase register number sizes from 5 to 7 tree | commitdiff
2021-01-29 Luke Kenneth Casso... syntax corrections, also size of maxvl was wrong tree | commitdiff
2021-01-29 Luke Kenneth Casso... add SVP64 RM (Remap) Record tree | commitdiff
2021-01-29 Luke Kenneth Casso... adjust SVP64RM class to output more PowerDecoder-friend... tree | commitdiff
2021-01-29 Luke Kenneth Casso... adjust how register copy/setup is done in PowerDecoder2 tree | commitdiff
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