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add code-fragment from microwatt helloworld
[soc.git]
/
src
/
2020-07-08
Luke Kenneth Casso...
add code-fragment from microwatt helloworld
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2020-07-08
Luke Kenneth Casso...
add a simple addis test (regression)
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2020-07-08
Luke Kenneth Casso...
copy binary loaded from disk into data memory as well
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2020-07-08
Cesar Strauss
Start the FSM-based ALU example.
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
add hello world binary test
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2020-07-07
Luke Kenneth Casso...
whoops error in test of dynamic parameter
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2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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2020-07-07
Luke Kenneth Casso...
code-shuffle on testing to prepare loading large files...
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2020-07-07
Cesar Strauss
Clear input data along with valid_i
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2020-07-07
Luke Kenneth Casso...
ordering of tests for OP_ATTN needed shuffling. seems...
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2020-07-07
Luke Kenneth Casso...
whoops got Function.NONE test wrong in PowerDecode2
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2020-07-07
Luke Kenneth Casso...
remove unneeded record field from logical_input_record
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2020-07-07
Luke Kenneth Casso...
debugging termination (OP_ATTN)
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2020-07-07
Luke Kenneth Casso...
update opcode map for OP_ATTN
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2020-07-07
Luke Kenneth Casso...
add halted condition in ISACaller, when attn instructio...
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2020-07-07
Luke Kenneth Casso...
debugging termination / OP_ATTN
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2020-07-07
Luke Kenneth Casso...
add ATTN unit test
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2020-07-07
Luke Kenneth Casso...
add core start/stop capability, and OP_ATTN support
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2020-07-07
Luke Kenneth Casso...
add in SPR test cases into test_issuer.py
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2020-07-06
Luke Kenneth Casso...
use ComMULOpSubset in mul pipeline
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2020-07-06
Luke Kenneth Casso...
remove alu unneeded op record data
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2020-07-06
Luke Kenneth Casso...
remove alu unneeded op record data
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commitdiff
2020-07-06
Luke Kenneth Casso...
remove alu unneeded op record data
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2020-07-06
Luke Kenneth Casso...
add mul unit to test_issuer
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2020-07-06
Luke Kenneth Casso...
add mul compunit
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2020-07-06
Luke Kenneth Casso...
whoops forgot that the mul pipeline is actually a pipel...
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2020-07-06
Luke Kenneth Casso...
do abs slightly differently in SelectableInt
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2020-07-06
Luke Kenneth Casso...
continue mul unit test debugging
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2020-07-06
Luke Kenneth Casso...
add MULS (signed) version of multiply
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commitdiff
2020-07-06
Luke Kenneth Casso...
improve debug for test_sim.py
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2020-07-06
Luke Kenneth Casso...
add mullw test to qemu sim
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2020-07-06
Luke Kenneth Casso...
fix SelectableInt abs
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2020-07-06
Luke Kenneth Casso...
add first simulator mul test
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2020-07-06
Luke Kenneth Casso...
investigating mul pipeline
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2020-07-06
Luke Kenneth Casso...
SelectableInt: make __mul__ return enough space to...
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2020-07-06
Luke Kenneth Casso...
first cut at mul test pipeline
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2020-07-06
Luke Kenneth Casso...
add first cut at fu mul pipeline
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2020-07-06
Luke Kenneth Casso...
adding mtspr tests
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2020-07-06
Luke Kenneth Casso...
adding OP_MTMSR test
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2020-07-06
Luke Kenneth Casso...
add mtmsr internal op
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2020-07-06
Luke Kenneth Casso...
add mtmsr internal op
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commitdiff
2020-07-06
Luke Kenneth Casso...
sort out initialisation of TstL0CacheBuffer in ldst...
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commitdiff
2020-07-06
Cesar Strauss
Assert n.ready_i at the beginning of the cycle
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commitdiff
2020-07-06
Cesar Strauss
Remove wait state to demonstrate zero-delay reception.
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commitdiff
2020-07-06
Cesar Strauss
Simplify waiting loops
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commitdiff
2020-07-06
Cesar Strauss
Finally add some well needed comments
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commitdiff
2020-07-06
Cesar Strauss
Simplify waiting loops
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2020-07-06
Cesar Strauss
Add some wait states in each process
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2020-07-06
Cesar Strauss
Negate inputs after use
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2020-07-06
Cesar Strauss
Add other tests
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2020-07-06
Cesar Strauss
Implement receiver
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2020-07-06
Cesar Strauss
Implement sender.
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2020-07-06
Cesar Strauss
Begin a new parallel test
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2020-07-05
Luke Kenneth Casso...
add mtmsr tests (fail)
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2020-07-05
Luke Kenneth Casso...
check trap compunit output properly
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2020-07-05
Luke Kenneth Casso...
check msr in trap test, fix OP_RFID
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2020-07-05
Luke Kenneth Casso...
add an illegal instruction trap test
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commitdiff
2020-07-05
Luke Kenneth Casso...
set up a trap function for microcode override
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2020-07-05
Luke Kenneth Casso...
big reorg on PowerDecoder2, actually Decode2Execute1Type
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2020-07-05
Luke Kenneth Casso...
stop debug output in power_decoder
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2020-07-05
Luke Kenneth Casso...
comments in power_regspec_map.py
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2020-07-05
Luke Kenneth Casso...
comment on spr2, not needed
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2020-07-05
Luke Kenneth Casso...
check xer_out not xer_in
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2020-07-05
Luke Kenneth Casso...
split out Decode2ToExecuteType fields involving registers
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2020-07-05
Luke Kenneth Casso...
sigh read and write xer detection, fix spr and trap...
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2020-07-05
Luke Kenneth Casso...
check spr1 in test spr compunit
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2020-07-05
Luke Kenneth Casso...
get/set slow spr in spr test_pipe_caller
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2020-07-05
Luke Kenneth Casso...
add first spr compunit test (not working yet)
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2020-07-05
Luke Kenneth Casso...
add SPR test case, commented out for now
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2020-07-05
Luke Kenneth Casso...
move valid signal out of Decode2ToExecute1Type and...
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2020-07-05
Luke Kenneth Casso...
add slow spr regfile regspec support
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2020-07-05
Luke Kenneth Casso...
remap SPR PowerISA numbers to internal SPR enum
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2020-07-05
Luke Kenneth Casso...
comment out SPR for now, needs SPR regfile
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2020-07-05
Luke Kenneth Casso...
add SPR compunit
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commitdiff
2020-07-05
Luke Kenneth Casso...
missing initialisation of disasm_start
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2020-07-05
Luke Kenneth Casso...
check NIA on trap fu test
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2020-07-05
Luke Kenneth Casso...
OP_RFID needs to read SRR0/1, OP_SC needs to write
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2020-07-05
Luke Kenneth Casso...
fix qemu trap test
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2020-07-04
Luke Kenneth Casso...
cater for illegal instruction (generates a trap)
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2020-07-04
Luke Kenneth Casso...
add sc back in
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2020-07-04
Luke Kenneth Casso...
comments in trap about exceptions using microcoding
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2020-07-04
Luke Kenneth Casso...
add pspec to test_core.py
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2020-07-04
Luke Kenneth Casso...
add pspec to test_core.py
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commitdiff
2020-07-04
Luke Kenneth Casso...
more rename spr1/spr2 to fast1/fast2
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2020-07-04
Luke Kenneth Casso...
whitespace
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2020-07-04
Luke Kenneth Casso...
more updating spr1/spr2 to fast1/fast2
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commitdiff
2020-07-04
Luke Kenneth Casso...
more updating spr1/spr2 to fast1/fast2
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commitdiff
2020-07-04
Luke Kenneth Casso...
rename spr1/spr2 to fast1/fast2 in branch
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2020-07-04
Luke Kenneth Casso...
update trap docstring
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2020-07-04
Luke Kenneth Casso...
use new consts module
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2020-07-04
Luke Kenneth Casso...
sorting out trap fastregs
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2020-07-04
Luke Kenneth Casso...
sort out trap test reg checking
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2020-07-04
Luke Kenneth Casso...
resolve spr names in ISACaller
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2020-07-04
Luke Kenneth Casso...
rename spr1 to fast1 in trap data
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2020-07-04
Luke Kenneth Casso...
sorting out fast/spr naming
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2020-07-04
Luke Kenneth Casso...
oops initialise Function Unit class with idx
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2020-07-04
Luke Kenneth Casso...
add first cookie-cut test_trap_compunit.py
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2020-07-04
Luke Kenneth Casso...
add gitignores
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2020-07-04
Luke Kenneth Casso...
debugging decoding of SPRs (fast)
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