missing self.
[soc.git] / src /
2021-05-01 Luke Kenneth Casso... missing self.
2021-05-01 Luke Kenneth Casso... resolve DriverConflict in TstL0CacheBuffer, really...
2021-04-30 Luke Kenneth Casso... debug and stop on mmu test_pipe_caller.py
2021-04-30 Luke Kenneth Casso... comments on dcache-to-mmu link
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py
2021-04-30 Luke Kenneth Casso... add option to use new mmu_cache_wb ConfigMemoryPortInte...
2021-04-30 Luke Kenneth Casso... hook up dcache wb_in/out to PortInterfaceBase Wishbone...
2021-04-30 Luke Kenneth Casso... sort out spblock 4k sram cell instance name to match...
2021-04-30 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=635
2021-04-30 Luke Kenneth Casso... better reporting on gpr comparisons
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and...
2021-04-29 Luke Kenneth Casso... comment out adding mmu and dcache to pspec in MMU FSM
2021-04-29 Luke Kenneth Casso... move dcache into Loadstore1
2021-04-27 Luke Kenneth Casso... add option to disable bus forwarding on SPRs and FAST...
2021-04-27 Luke Kenneth Casso... add option to enable/disable bus forwarding mode on...
2021-04-27 Luke Kenneth Casso... return read data out from Loadstore1 only when valid
2021-04-26 Luke Kenneth Casso... hook up MSR into MMU (TODO, use a lot less bits)
2021-04-26 Luke Kenneth Casso... simple regression dcache test was faulty. wishbone...
2021-04-26 Luke Kenneth Casso... comment read ack in sram
2021-04-26 Luke Kenneth Casso... incorrect indentation in dcache rams
2021-04-26 Luke Kenneth Casso... simplify dcache test
2021-04-25 Luke Kenneth Casso... spelling mistake
2021-04-25 Luke Kenneth Casso... remove RegStage1.real_adr temporary from dcache
2021-04-25 Luke Kenneth Casso... do not overwrite parameter ra in dcache
2021-04-25 Luke Kenneth Casso... comment out dcache_store from test, not the problem
2021-04-25 Luke Kenneth Casso... remove unneeded code
2021-04-25 Luke Kenneth Casso... read req in wb_in.stall, dcache
2021-04-25 Cesar StraussShift-out skipped mask bits for both crpred and intpred
2021-04-25 Luke Kenneth Casso... add single regression test for dcache
2021-04-25 Luke Kenneth Casso... add TODO comment in dcache
2021-04-25 Luke Kenneth Casso... move Signals in dcache to relevant context
2021-04-25 Luke Kenneth Casso... dcache Elif used where If should have been
2021-04-25 Luke Kenneth Casso... whoops should be cyc & ~ack
2021-04-25 Luke Kenneth Casso... hard-code dcache stall signal to non-pipelined mode
2021-04-24 Luke Kenneth Casso... increase memory size in dcache test
2021-04-24 Luke Kenneth Casso... increase size of random dcache testing by 10
2021-04-24 Luke Kenneth Casso... fix errors in dcache unit test
2021-04-24 Luke Kenneth Casso... whitespace
2021-04-24 Luke Kenneth Casso... remove code moved to openpower-isa repo
2021-04-23 Luke Kenneth Casso... add comments on TestIssuer TestRunner
2021-04-23 Luke Kenneth Casso... comment tests back in
2021-04-23 Luke Kenneth Casso... fix import error
2021-04-23 Luke Kenneth Casso... error in setting fast regs test values
2021-04-23 Luke Kenneth Casso... import from openpower.tests
2021-04-23 Luke Kenneth Casso... whitespace
2021-04-23 Luke Kenneth Casso... move logical tests to openpower.test
2021-04-23 Luke Kenneth Casso... add trap test cases
2021-04-23 Luke Kenneth Casso... move SPR tests to openpower.test
2021-04-23 Luke Kenneth Casso... move branch test cases to openpower.test
2021-04-23 Luke Kenneth Casso... move LDST tests to openpower.test
2021-04-23 Luke Kenneth Casso... move mul tests to openpower.test
2021-04-23 Luke Kenneth Casso... move div tests to openpower.test
2021-04-23 Luke Kenneth Casso... move div tests to openpower.test
2021-04-23 Luke Kenneth Casso... move ALU test cases to openpower.test
2021-04-23 Luke Kenneth Casso... move MMU Testcase to openpower.test
2021-04-23 Luke Kenneth Casso... move CR test cases to openpower.test
2021-04-23 Luke Kenneth Casso... move shiftrot test cases to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa
2021-04-23 Luke Kenneth Casso... move to import from openpower-isa for reg enums
2021-04-23 Luke Kenneth Casso... remove pseudo, moved to openpower-isa
2021-04-23 Luke Kenneth Casso... remove simulator directory, moved to openpower-isa
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... correct migration of openpower-isa
2021-04-23 Luke Kenneth Casso... more openpower import conversion
2021-04-23 Luke Kenneth Casso... more openpower import conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-23 Luke Kenneth Casso... move over to openpower-isa repo
2021-04-23 Luke Kenneth Casso... move over to openpower-isa
2021-04-23 Luke Kenneth Casso... moving more over to openpower-isa repo
2021-04-23 Luke Kenneth Casso... removing more as moved over to openpower-isa
2021-04-23 Luke Kenneth Casso... submodule update
2021-04-22 Luke Kenneth Casso... add debugging and buffering to CacheRam
2021-04-22 Luke Kenneth Casso... whitespace
2021-04-22 Luke Kenneth Casso... r1.end_row_ix off-by-one in dcache
2021-04-22 Luke Kenneth Casso... sync missing in dcache
2021-04-22 Luke Kenneth Casso... dcache.py code-comments
2021-04-22 Luke Kenneth Casso... cleanup dcache
2021-04-22 Luke Kenneth Casso... error using sync, should have been comb
2021-04-22 Cesar StraussImplement CR predication
2021-04-21 Cesar StraussCR sub-fields are stored in MSB0 order
2021-04-21 Luke Kenneth Casso... experimenting with dcache
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu
2021-04-21 Cesar StraussAdd CR predication test case for TestIssuer
2021-04-21 Cesar StraussFix comment in CR predication test case
2021-04-21 Cesar StraussFix sense of "invert" signal
2021-04-20 Luke Kenneth Casso... add enable MMU option to issuer_verilog.py
2021-04-20 Luke Kenneth Casso... cannot pass in arguments to Core - must be done with...
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2021-04-20 Luke Kenneth Casso... add wishbone sram.py (move from nmigen-soc)
2021-04-19 Luke Kenneth Casso... give independent names to spblock512w64b8ws
2021-04-18 Luke Kenneth Casso... give spblock512 a name as a submodule
2021-04-18 Luke Kenneth Casso... create signal on test_issuer which gives PLL clk_sel_i...
2021-04-18 Luke Kenneth Casso... rename SPBlock_512W64B8W to lowercase
2021-04-18 Luke Kenneth Casso... submodule update
2021-04-18 Luke Kenneth Casso... rename PLL pins to match LIP6.fr PLL
2021-04-18 Luke Kenneth Casso... core_stopped_i unused: remove
2021-04-18 Luke Kenneth Casso... submodule update
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