soc.git
13 months agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Mon, 24 Aug 2020 00:48:16 +0000 (17:48 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

13 months agodcache.py commit first full tranlation pass, about five percent left
Cole Poirier [Mon, 24 Aug 2020 00:46:21 +0000 (17:46 -0700)]
dcache.py commit first full tranlation pass, about five percent left
undone as I don't understand how to do it and need help

13 months agoupdate copyright notices to include additional primary author
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 21:07:33 +0000 (22:07 +0100)]
update copyright notices to include additional primary author
(michael, please make sure to be properly informed on copyright law.
the git commit logs are the "ultimate" record, and simply being just one
of the authors does not mean that you can take the entire code and re-license
it under your own license.  you can only take the portions that *you* wrote)

13 months agoadd load algebraic immediate unit test
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 20:57:10 +0000 (21:57 +0100)]
add load algebraic immediate unit test

13 months agoadd algebraic ld tests lwax, lwaux
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 20:39:25 +0000 (21:39 +0100)]
add algebraic ld tests lwax, lwaux

13 months agoAdd copyright to files I primarily authored in simulator/
Michael Nolan [Sun, 23 Aug 2020 20:06:24 +0000 (16:06 -0400)]
Add copyright to files I primarily authored in simulator/

13 months agoAdd copyright to files in fu/ that I was the primary author on
Michael Nolan [Sun, 23 Aug 2020 20:04:13 +0000 (16:04 -0400)]
Add copyright to files in fu/ that I was the primary author on

13 months agoAdd copyright statement to power_decoder.py
Michael Nolan [Sun, 23 Aug 2020 19:51:32 +0000 (15:51 -0400)]
Add copyright statement to power_decoder.py

Michael Copyright

13 months agobring "core stopped" signal out through DMI interface
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 19:49:13 +0000 (20:49 +0100)]
bring "core stopped" signal out through DMI interface

13 months agoadd in DMI "stat" loop which monitors core "stopping"
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 19:36:58 +0000 (20:36 +0100)]
add in DMI "stat" loop which monitors core "stopping"

13 months agoAllow an empty style, and passing default styles as arguments
Cesar Strauss [Sun, 23 Aug 2020 19:26:20 +0000 (16:26 -0300)]
Allow an empty style, and passing default styles as arguments

This permits to entirely avoid passing a style structure, if only
the root selector is needed.

14 months agoAdd comment node type
Cesar Strauss [Sun, 23 Aug 2020 18:31:12 +0000 (15:31 -0300)]
Add comment node type

14 months agoAdd base and display styles
Cesar Strauss [Sun, 23 Aug 2020 18:06:21 +0000 (15:06 -0300)]
Add base and display styles

14 months agoApply style from node own name
Cesar Strauss [Sun, 23 Aug 2020 17:51:35 +0000 (14:51 -0300)]
Apply style from node own name

14 months agoAdd color style
Cesar Strauss [Sun, 23 Aug 2020 17:44:54 +0000 (14:44 -0300)]
Add color style

14 months agoCollect styles from the tuple
Cesar Strauss [Sun, 23 Aug 2020 17:14:52 +0000 (14:14 -0300)]
Collect styles from the tuple

14 months agoPropagate the root style to all signals
Cesar Strauss [Sun, 23 Aug 2020 16:17:24 +0000 (13:17 -0300)]
Propagate the root style to all signals

Begin by prepending the default module path to all signal names.

14 months agocomment why litex sim mem map is altered
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 14:18:54 +0000 (15:18 +0100)]
comment why litex sim mem map is altered

14 months agomultiply does not have invert_in, zero_a or invert_out
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 11:32:10 +0000 (12:32 +0100)]
multiply does not have invert_in, zero_a or invert_out

14 months agorename invert_a to invert_in because logical inverts RB
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:53:25 +0000 (00:53 +0100)]
rename invert_a to invert_in because logical inverts RB

14 months agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:46:13 +0000 (00:46 +0100)]
update submodule

14 months agoload bios not 1.bin unit test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:46:00 +0000 (00:46 +0100)]
load bios not 1.bin unit test

14 months agoadd extra div regression tests
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:45:28 +0000 (00:45 +0100)]
add extra div regression tests

14 months agoMove comments to the docstring
Cesar Strauss [Sat, 22 Aug 2020 21:13:51 +0000 (18:13 -0300)]
Move comments to the docstring

14 months agoWalk the DOM and emit the trace names
Cesar Strauss [Sat, 22 Aug 2020 19:14:53 +0000 (16:14 -0300)]
Walk the DOM and emit the trace names

Descend into the children of each group, while emitting the group
delimiters.

14 months agoadd eqv to logical unit test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 15:10:03 +0000 (16:10 +0100)]
add eqv to logical unit test

14 months agoadd nor and nand to unit test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 15:09:06 +0000 (16:09 +0100)]
add nor and nand to unit test

14 months agomoved to div pipe temporarily in compunits
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 15:07:22 +0000 (16:07 +0100)]
moved to div pipe temporarily in compunits

14 months agobug in andc and orc, complement was taking place on RA not RB
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 14:39:29 +0000 (15:39 +0100)]
bug in andc and orc, complement was taking place on RA not RB

14 months agoextend addis test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 14:11:46 +0000 (15:11 +0100)]
extend addis test

14 months agoadd andc and orc tests, failing because RB needs inversion not RA
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 14:11:25 +0000 (15:11 +0100)]
add andc and orc tests, failing because RB needs inversion not RA

14 months agomodsd bug, https://bugs.libre-soc.org/show_bug.cgi?id=471
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 13:01:26 +0000 (14:01 +0100)]
modsd bug, https://bugs.libre-soc.org/show_bug.cgi?id=471

14 months agoFirst draft of a mini-language to describe GTKWave documents
Cesar Strauss [Sat, 22 Aug 2020 12:13:21 +0000 (09:13 -0300)]
First draft of a mini-language to describe GTKWave documents

Uses a split CSS + DOM approach, where style is separated from content.
For the moment, only syntax and semantics definitions are proposed.
Implementation should be the next step.

14 months agosubmodule update
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 12:18:03 +0000 (13:18 +0100)]
submodule update

14 months agoadd regression test for nonzero addis
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 11:24:29 +0000 (12:24 +0100)]
add regression test for nonzero addis

14 months agoadd means to run microwatt test binaries
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 11:23:23 +0000 (12:23 +0100)]
add means to run microwatt test binaries

14 months agor0 zero tests on addis, fails
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 11:09:19 +0000 (12:09 +0100)]
r0 zero tests on addis, fails

14 months agoinvestigating litex sdrinit function
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 10:35:00 +0000 (11:35 +0100)]
investigating litex sdrinit function

14 months agoadd pseudo-op conversion
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 10:32:06 +0000 (11:32 +0100)]
add pseudo-op conversion

14 months agoadd start of litex bios counter loop
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 10:26:22 +0000 (11:26 +0100)]
add start of litex bios counter loop

14 months agoremove extraneous comments
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 21:07:02 +0000 (22:07 +0100)]
remove extraneous comments

14 months agotesting 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 21:05:12 +0000 (22:05 +0100)]
testing 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*

14 months agotypo fix in test_l0_cache_buffer2.py
Tobias Platen [Fri, 21 Aug 2020 18:49:14 +0000 (20:49 +0200)]
typo fix in test_l0_cache_buffer2.py

14 months agodcache.py fix asserts, use backslash and two strings, one per line,
Cole Poirier [Fri, 21 Aug 2020 18:12:57 +0000 (11:12 -0700)]
dcache.py fix asserts, use backslash and two strings, one per line,
fixes rest of https://bugs.libre-soc.org/show_bug.cgi?id=469#c2

14 months agodcache.py replace functions that return signals with constants, generate
Cole Poirier [Fri, 21 Aug 2020 18:07:21 +0000 (11:07 -0700)]
dcache.py replace functions that return signals with constants, generate
ranges from constans instead of same functions returned signals, remove
default values from function args, fixes most of https://bugs.libre-soc.org/show_bug.cgi?id=469#c2

14 months agowb_types fix typo
Cole Poirier [Fri, 21 Aug 2020 18:06:52 +0000 (11:06 -0700)]
wb_types fix typo

14 months agoconnect TestCachedMemoryPortInterface to LDSTSplitter
Tobias Platen [Fri, 21 Aug 2020 16:41:54 +0000 (18:41 +0200)]
connect TestCachedMemoryPortInterface to LDSTSplitter

14 months agoget litex sim enabled with 32-bit wishbone bus
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 15:37:10 +0000 (16:37 +0100)]
get litex sim enabled with 32-bit wishbone bus

14 months agold/st bus reduction test operational
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 14:24:06 +0000 (15:24 +0100)]
ld/st bus reduction test operational

14 months agofirst test of down-converted load/store from 64 to 32 bit
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 12:06:03 +0000 (13:06 +0100)]
first test of down-converted load/store from 64 to 32 bit

14 months agofirst test of down-converted load/store from 64 to 32 bit
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 12:05:45 +0000 (13:05 +0100)]
first test of down-converted load/store from 64 to 32 bit

14 months agoadd in WishboneDownConvert into LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 11:41:42 +0000 (12:41 +0100)]
add in WishboneDownConvert into LoadStoreUnitInterface

14 months agocomment formatting
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 11:00:15 +0000 (12:00 +0100)]
comment formatting

14 months agoremove default values
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 10:59:46 +0000 (11:59 +0100)]
remove default values

14 months agojust range(the_constant)
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 10:57:17 +0000 (11:57 +0100)]
just range(the_constant)

14 months agoMUL pipeline WIP: mullw and mullwu covered.
Samuel A. Falvo II [Fri, 21 Aug 2020 03:20:20 +0000 (20:20 -0700)]
MUL pipeline WIP: mullw and mullwu covered.

14 months agoMUL pipeline: account for overflow flags. WIP
Samuel A. Falvo II [Fri, 21 Aug 2020 02:54:20 +0000 (19:54 -0700)]
MUL pipeline: account for overflow flags.  WIP

14 months agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Fri, 21 Aug 2020 02:46:37 +0000 (19:46 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

14 months agodcache.py commit today and yesterday's progress (sorry for the delay,
Cole Poirier [Fri, 21 Aug 2020 02:44:41 +0000 (19:44 -0700)]
dcache.py commit today and yesterday's progress (sorry for the delay,
unexpected circumstances led me to not be able to commit yesterday)

14 months agoMUL pipeline proofs: mulli / mullw WIP.
Samuel A. Falvo II [Fri, 21 Aug 2020 01:32:17 +0000 (18:32 -0700)]
MUL pipeline proofs: mulli / mullw WIP.

14 months agoMUL pipeline proof: muldw(u)
Samuel A. Falvo II [Thu, 20 Aug 2020 23:58:11 +0000 (16:58 -0700)]
MUL pipeline proof: muldw(u)

14 months agoMUL pipeline proof: signed mulhw
Samuel A. Falvo II [Thu, 20 Aug 2020 22:30:17 +0000 (15:30 -0700)]
MUL pipeline proof: signed mulhw

14 months agostart wiring TestCachedMemoryPortInterface
Tobias Platen [Thu, 20 Aug 2020 18:47:39 +0000 (20:47 +0200)]
start wiring TestCachedMemoryPortInterface

14 months agotestcase refactoring
Tobias Platen [Thu, 20 Aug 2020 18:11:56 +0000 (20:11 +0200)]
testcase refactoring

14 months agoadd new class TestCachedMemoryPortInterface
Tobias Platen [Thu, 20 Aug 2020 17:34:32 +0000 (19:34 +0200)]
add new class TestCachedMemoryPortInterface

14 months agobugfix wishbone downconvert using wb sram 64-to-32 test
Luke Kenneth Casson Leighton [Thu, 20 Aug 2020 14:28:12 +0000 (15:28 +0100)]
bugfix wishbone downconvert using wb sram 64-to-32 test

14 months agoadd a wishbone upconverter
Luke Kenneth Casson Leighton [Thu, 20 Aug 2020 13:20:15 +0000 (14:20 +0100)]
add a wishbone upconverter

14 months agorename and document fields in shift_rot proof
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 22:03:54 +0000 (23:03 +0100)]
rename and document fields in shift_rot proof

14 months agocomments in dcache
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 18:58:12 +0000 (19:58 +0100)]
comments in dcache

14 months agomore subtle interactions between wishbone bus when there are delays,
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 18:02:30 +0000 (19:02 +0100)]
more subtle interactions between wishbone bus when there are delays,
LD/ST CompUnit and PortInterface

14 months agobit of a reorg of mul proof, tracking down missing
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 06:24:58 +0000 (07:24 +0100)]
bit of a reorg of mul proof, tracking down missing
Assume op.is_32bit == 0 for OP_MUL_H32

14 months agomove long mul tests to separate unit test
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 06:24:00 +0000 (07:24 +0100)]
move long mul tests to separate unit test

14 months agouse "Mask" class which is more gate-efficient than (1<<x)-1
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 04:45:21 +0000 (05:45 +0100)]
use "Mask" class which is more gate-efficient than (1<<x)-1

14 months agoWIP: OP_MUL proofs started.
Samuel A. Falvo II [Wed, 19 Aug 2020 04:12:19 +0000 (21:12 -0700)]
WIP: OP_MUL proofs started.

I am out of my league.  Cannot figure out how to make proof pass.
Committing latest incarnation of proof code.

14 months agoset up StageChain of 3 mul stages
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 00:15:33 +0000 (01:15 +0100)]
set up StageChain of 3 mul stages

14 months agofu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov change rb
Cole Poirier [Tue, 18 Aug 2020 21:15:20 +0000 (14:15 -0700)]
fu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov change rb
dividend from randint(0,1) to randint((-1 << 31), (1 << 31) - 1)

14 months agoadd testcase for LDSTSplitter using PortInterface
Tobias Platen [Tue, 18 Aug 2020 17:50:43 +0000 (19:50 +0200)]
add testcase for LDSTSplitter using PortInterface

14 months agofix spr state test
Luke Kenneth Casson Leighton [Tue, 18 Aug 2020 11:39:51 +0000 (12:39 +0100)]
fix spr state test

14 months agoadd comment in dcache.py
Luke Kenneth Casson Leighton [Tue, 18 Aug 2020 00:34:15 +0000 (01:34 +0100)]
add comment in dcache.py

14 months agodcache.py commit today's progress on translating dcache.vhdl
Cole Poirier [Mon, 17 Aug 2020 23:46:12 +0000 (16:46 -0700)]
dcache.py commit today's progress on translating dcache.vhdl

14 months agoCreate file experiment/wb_types.py to mirror microwatt wishbone_types.vhdl
Cole Poirier [Mon, 17 Aug 2020 23:44:55 +0000 (16:44 -0700)]
Create file experiment/wb_types.py to mirror microwatt wishbone_types.vhdl

14 months agomove Mask to nmutil
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 11:10:33 +0000 (12:10 +0100)]
move Mask to nmutil

14 months agoturn SelectableInt less/greater into signed versions.
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:59:49 +0000 (10:59 +0100)]
turn SelectableInt less/greater into signed versions.
may have ramifications as use of these operators assumes
unsigned

14 months agouse longer memtest in litex sim
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:59:04 +0000 (10:59 +0100)]
use longer memtest in litex sim

14 months agoadjust litex bios cmp test
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:58:20 +0000 (10:58 +0100)]
adjust litex bios cmp test

14 months agofix signed variants of cmp in alu
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:57:30 +0000 (10:57 +0100)]
fix signed variants of cmp in alu

14 months agoadd new cmp test for alu
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:56:48 +0000 (10:56 +0100)]
add new cmp test for alu

14 months agouse shift module in mmu. to be moved to nmutil
Luke Kenneth Casson Leighton [Mon, 17 Aug 2020 09:40:14 +0000 (10:40 +0100)]
use shift module in mmu. to be moved to nmutil

14 months agommu.py fix formatting 80 char limit
Cole Poirier [Sun, 16 Aug 2020 18:07:02 +0000 (11:07 -0700)]
mmu.py fix formatting 80 char limit

14 months agoattempting to track down bug in litex bios memtest
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 17:29:12 +0000 (18:29 +0100)]
attempting to track down bug in litex bios memtest

14 months agoread delay on getting regfile data
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 16:27:01 +0000 (17:27 +0100)]
read delay on getting regfile data

14 months agolimit debug reporting in litex sim to range of pc
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 14:28:15 +0000 (15:28 +0100)]
limit debug reporting in litex sim to range of pc

14 months agocmp test from litex bios
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 14:27:56 +0000 (15:27 +0100)]
cmp test from litex bios

14 months agoremove vhdl comments
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 13:25:41 +0000 (14:25 +0100)]
remove vhdl comments

14 months agouse simple one-line mask-generation
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 13:22:36 +0000 (14:22 +0100)]
use simple one-line mask-generation

14 months agofix LD/ST pimem issue with rising_edge detection
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 12:16:22 +0000 (13:16 +0100)]
fix LD/ST pimem issue with rising_edge detection

14 months agomissing vars, spelling corrections
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 10:25:55 +0000 (11:25 +0100)]
missing vars, spelling corrections

14 months agobig reorg, shuffle code to functions, makes the FSM clearer
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 10:11:48 +0000 (11:11 +0100)]
big reorg, shuffle code to functions, makes the FSM clearer

14 months agospelling error, move perm_ok to local
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:51:32 +0000 (10:51 +0100)]
spelling error, move perm_ok to local

14 months agomore comment removal
Luke Kenneth Casson Leighton [Sun, 16 Aug 2020 09:47:39 +0000 (10:47 +0100)]
more comment removal