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add an SRAM and wishbone to add test (makes it bigger)
[soclayout.git] / experiments10_verilog /
2021-04-14 Luke Kenneth Casso... add an SRAM and wishbone to add test (makes it bigger) tree | commitdiff
2021-04-14 Luke Kenneth Casso... connect up boundary scan to inputs/outputs tree | commitdiff
2021-04-13 Luke Kenneth Casso... use METAL10 for topRoutingLayer tree | commitdiff
2021-04-13 Luke Kenneth Casso... whoops forgot settings.py tree | commitdiff
2021-04-12 Luke Kenneth Casso... set routingGauge manually tree | commitdiff
2021-04-12 Luke Kenneth Casso... enable HFNS in adder tree | commitdiff
2021-04-12 Luke Kenneth Casso... include (but do not use) FreePDK45 in experiments10 tree | commitdiff
2021-04-12 Luke Kenneth Casso... different FreePDK45 experiments10 chip size tree | commitdiff
2021-04-12 Luke Kenneth Casso... experimentation to get experiment10_verilog work with... tree | commitdiff
2021-04-12 Luke Kenneth Casso... add FreePDK45 experiments10_verilog doDesign.py tree | commitdiff
2021-04-12 Luke Kenneth Casso... add FreePDK45 variant of experiments10_verilog tree | commitdiff
2021-04-12 Luke Kenneth Casso... rename sys_clk in adder test experiments10_verilog... tree | commitdiff
2021-04-12 Luke Kenneth Casso... rename JTAG port in adder test experiments10_verilog... tree | commitdiff
2021-04-12 Luke Kenneth Casso... back to "working" verilog add tree | commitdiff
2021-04-09 Luke Kenneth Casso... sigh, broken experiment10_verilog tree | commitdiff
2021-04-09 Luke Kenneth Casso... whitespace cleanup tree | commitdiff
2021-04-09 Luke Kenneth Casso... pad name starts with p_ tree | commitdiff
2021-04-09 Luke Kenneth Casso... rename design of experiments10 to match ls180 chip... tree | commitdiff
2021-04-02 Luke Kenneth Casso... experiment with nmigen verilog generation tree | commitdiff