correctly set SR_EA bit for all vector physical supervisor tests

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index b27126807cd3ef3ced1f5e5121486cb20177073d..2440cbbf745e9a8fa85988cc134c55a828829855 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index 8dac90d3bfaacf5671313f83d883db6aabb085ea..c61d4d9f2c1976fdbc3274ac92a4e6796428ae79 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index cddae2934b0a7d32be03d5541b260572c7fa2d1c..ff8cee10b142abdaddc0ac523fdbb2400a66cd72 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index d57aecae0b6849ed6b543c7e62b5b553f5134fa3..4cfa1e0c3cc5122d9ee93515c03f706834f0081f 100644 (file)
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -11,6 +11,8 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
+
   mfpcr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index de026f4c10d6ea02ac6faa2395e4eeff984fa714..9bb586b5190f098e37208ea34f83ba00cb9adbb2 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index e612a8623f2886cbbf3b56c5b50c5cdfb7dbc804..120facc9c5b39c6fb09eb4428e15cf21739516c5 100644 (file)
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -11,6 +11,8 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
+
   mfpcr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 2cc42bce7bf53ca60351ac4393f6f910f85c4a5e..aff6e1ae27cc9ad0c27f89b1e50933a0ec033808 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index ead6c2c0ed6a5a717f00fbcdafc43e5c434e510e..20249e3334d60ddeac8d0c70745cdd9150241c4c 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 3ea11e9d1b0e459d8d1d054d950f40efe7ec980f..b353c431bb559727615eef5a3d1ad177e7f50870 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index fbbc0cd4c4ff2f2e13ecda598300dbd4038e4727..227955c9d964ccf5d1c6cfe23cd90db5f8a6db08 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index d76f26c3f5469c1a9d9b51798348e78b2ff378ae..85667e42c04314dfc058f54a1c16ad5cb23e3314 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 3f04f6013e3d7f852e59288c6c89782b63fcda75..64a75081ec87e467617ed4aca5c678a9c6fa29f7 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler