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icache.py fix several subtle bugs that were lines that I had missed from
[soc.git]
/
src
/
soc
/
bus
/
2020-09-05
Luke Kenneth Casso...
add simple GPIO wishbone bus to litex sim.py
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
move wb read/write to separate util test library and...
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
add simple wishbone GPIO peripheral
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commitdiff
2020-08-21
Luke Kenneth Casso...
ld/st bus reduction test operational
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2020-08-21
Luke Kenneth Casso...
first test of down-converted load/store from 64 to...
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commitdiff
2020-08-21
Luke Kenneth Casso...
first test of down-converted load/store from 64 to...
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commitdiff
2020-08-21
Luke Kenneth Casso...
add in WishboneDownConvert into LoadStoreUnitInterface
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commitdiff
2020-08-21
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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commitdiff
2020-08-20
Luke Kenneth Casso...
bugfix wishbone downconvert using wb sram 64-to-32...
tree
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commitdiff
2020-08-20
Luke Kenneth Casso...
add a wishbone upconverter
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commitdiff
2020-07-29
Jacob Lifshay
add __init__.py to all source directories
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commitdiff
2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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commitdiff
2020-07-22
Jacob Lifshay
format code
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commitdiff
2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-07-07
Luke Kenneth Casso...
whoops error in test of dynamic parameter
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commitdiff
2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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commitdiff
2020-07-07
Luke Kenneth Casso...
code-shuffle on testing to prepare loading large files...
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commitdiff
2020-07-01
Luke Kenneth Casso...
minor reorg on how Bus and Config classes are set up
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commitdiff
2020-06-29
Luke Kenneth Casso...
fetch instructions from bare wishbone fetch unit
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commitdiff
2020-06-28
Luke Kenneth Casso...
read from instruction memory using FetchUnitInterface
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commitdiff
2020-06-28
Luke Kenneth Casso...
sram address do not cut by LSBs
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commitdiff
2020-06-27
Luke Kenneth Casso...
make Memory accessible via TestSRAMBareLoadStoreUnit
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commitdiff
2020-06-26
Luke Kenneth Casso...
investigating why write-enable not getting passed through
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commitdiff
2020-06-26
Luke Kenneth Casso...
whoops forgot to call parent elaborate
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commitdiff
2020-06-26
Luke Kenneth Casso...
add test of SRAM through wishbone bus
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commitdiff
2020-06-26
Luke Kenneth Casso...
code-morph which redirects lsmem unit test through...
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commitdiff
2020-06-26
Luke Kenneth Casso...
add a test SRAM that lives behind a minerva LoadStoreUn...
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commitdiff
2020-06-20
Luke Kenneth Casso...
expand Memory width to 64 and granularity to 16 in...
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commitdiff
2020-06-20
Luke Kenneth Casso...
add asserts to check data output is correct
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commitdiff
2020-06-20
Luke Kenneth Casso...
add test_sram_wishbone.py
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commitdiff