git.libre-soc.org Git - soc.git/history - src/soc/clock/dummypll.py

2021-06-03	Luke Kenneth Casso...	rename ref to ref_v in PLL due to ref being a verilog...	blob \| commitdiff \| raw
2021-05-27	Luke Kenneth Casso...	adjust PLL connections looking for coriolis2 issue	blob \| commitdiff \| raw \| diff to current
2021-05-26	Luke Kenneth Casso...	rename PLL signals	blob \| commitdiff \| raw \| diff to current
2021-05-24	Luke Kenneth Casso...	change name of submodule to real_pll	blob \| commitdiff \| raw \| diff to current
2021-05-24	Luke Kenneth Casso...	match up PLL names	blob \| commitdiff \| raw \| diff to current
2021-05-22	Luke Kenneth Casso...	update PLL to use Instance	blob \| commitdiff \| raw \| diff to current
2021-04-18	Luke Kenneth Casso...	create signal on test_issuer which gives PLL clk_sel_i...	blob \| commitdiff \| raw \| diff to current
2021-04-18	Luke Kenneth Casso...	rename PLL pins to match LIP6.fr PLL	blob \| commitdiff \| raw \| diff to current
2020-11-13	Luke Kenneth Casso...	reduce clkcsel ls180 width (2 pins), rename pll_18...	blob \| commitdiff \| raw \| diff to current
2020-11-13	Luke Kenneth Casso...	rename and add pll lock signal to ls180	blob \| commitdiff \| raw \| diff to current
2020-11-10	Luke Kenneth Casso...	remove ClockSelect module, use DummyPLL	blob \| commitdiff \| raw \| diff to current
2020-11-10	Luke Kenneth Casso...	add separate DummyPLL module, according to API discussed at	blob \| commitdiff \| raw \| diff to current