2020-09-07 |
Luke Kenneth Casso... | bit of a big reorg of data structures |
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2020-08-15 |
Luke Kenneth Casso... | clear compalu data latch always on issue |
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2020-08-14 |
Luke Kenneth Casso... | remove latchregister, use sync to capture compunit... |
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2020-08-14 |
Luke Kenneth Casso... | sync on alu results in compalu |
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2020-08-13 |
Luke Kenneth Casso... | code-shuffle |
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2020-08-13 |
Luke Kenneth Casso... | sync on reset in compalu |
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2020-08-13 |
Luke Kenneth Casso... | another sync to cut latency |
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2020-08-13 |
Luke Kenneth Casso... | remove latchregister, sync src oper_i into MultiCompUnit |
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2020-08-13 |
Luke Kenneth Casso... | minor tidyup on alu compunit: |
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2020-08-13 |
Luke Kenneth Casso... | plenty of time to wait for operand, so use "sync" in... |
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2020-08-09 |
Luke Kenneth Casso... | compalu combinatorial loop detected |
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2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
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2020-07-25 |
Luke Kenneth Casso... | going on a bit of a "naming" spree, this for Jean-Paul... |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-11 |
Luke Kenneth Casso... | sort out core write latching: gate by busy, and use... |
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2020-07-11 |
Luke Kenneth Casso... | * clarifying core function unit enable |
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2020-07-02 |
Luke Kenneth Casso... | allow ALU names to propagate through from FU to CompUni... |
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2020-06-11 |
Luke Kenneth Casso... | even more complexity in CompALUMulti, to deal with... |
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2020-06-09 |
Cesar Strauss | Avoid a combinatorial loop on valid_o |
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2020-06-06 |
Luke Kenneth Casso... | allow Mem initialisation in ISACaller |
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2020-06-06 |
Luke Kenneth Casso... | LDSTCompUnit test data structures linked up, starting... |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-02 |
Luke Kenneth Casso... | argh - bad hack, detecting when there are no registers... |
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2020-06-01 |
Luke Kenneth Casso... | sigh - another instance where write-mask needed to... |
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2020-05-31 |
Luke Kenneth Casso... | remove unneeded imports |
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2020-05-31 |
Luke Kenneth Casso... | split out compalu unit tests to separate module (gettin... |
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2020-05-31 |
Luke Kenneth Casso... | HA! found a bug in MultiCompUnit handling of write... |
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2020-05-30 |
Luke Kenneth Casso... | add in write-mask into MultiCompUnit and MCU-ALU unit... |
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2020-05-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-05-30 |
Luke Kenneth Casso... | create a write-mask, anything with an "ok" in the Recor... |
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2020-05-30 |
Luke Kenneth Casso... | allow MultiCompUnit outputs to be Records, to capture... |
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2020-05-30 |
Luke Kenneth Casso... | add read-mask to MultiCompUnit |
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2020-05-30 |
Luke Kenneth Casso... | code-shuffle / comments |
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2020-05-30 |
Luke Kenneth Casso... | mess - but a functional mess. ALU-MultiCompUnit semi... |
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2020-05-30 |
Luke Kenneth Casso... | grab other results from ALU pipeline in compunit test |
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2020-05-30 |
Luke Kenneth Casso... | still experimenting with ALU-CompUnit interaction |
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2020-05-29 |
Luke Kenneth Casso... | trigger ALU ready when operands ready |
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2020-05-29 |
Luke Kenneth Casso... | trigger read ALU ready/valid from latch as well |
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2020-05-29 |
Luke Kenneth Casso... | use a latch to communicate read/valid output from ALU |
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2020-05-29 |
Luke Kenneth Casso... | latch all output on ALU output valid |
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2020-05-29 |
Luke Kenneth Casso... | create read-done pulse |
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2020-05-29 |
Luke Kenneth Casso... | write-release moves out of "ALU valid" due to using... |
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2020-05-29 |
Luke Kenneth Casso... | signal start of request from when ALU triggers result... |
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2020-05-29 |
Luke Kenneth Casso... | create rising pulse from ALU valid |
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2020-05-29 |
Luke Kenneth Casso... | names of attributes needs to be dest_o not dest_i |
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2020-05-29 |
Cesar Strauss | Allow immediate assertion of go in the same cycle as rel |
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2020-05-29 |
Cesar Strauss | Correct typo |
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2020-05-29 |
Cesar Strauss | Send a one-clock "go" pulse after a configurable number... |
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2020-05-28 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-05-28 |
Luke Kenneth Casso... | add quick test of 3-operand DummyALU in MultiCompALU |
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2020-05-28 |
Luke Kenneth Casso... | debugging test_alu_compunit.py |
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2020-05-28 |
Cesar Strauss | Check that rd rises after issue_i, unless it's immediate |
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2020-05-28 |
Cesar Strauss | Store and present parameters together with issue_i |
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2020-05-27 |
Cesar Strauss | Move test case parameters to an "operation" member... |
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2020-05-27 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-05-27 |
Cesar Strauss | Remove the monitor process |
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2020-05-25 |
Cesar Strauss | Check that busy_o doesn't rise on its own |
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2020-05-25 |
Cesar Strauss | Implement the issue_i/busy_o protocol check. |
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2020-05-25 |
Cesar Strauss | Move process list to CompUnitParallelTest |
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2020-05-25 |
Luke Kenneth Casso... | update comments on compalu_multi.py |
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2020-05-25 |
Luke Kenneth Casso... | add some more stub comments |
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2020-05-25 |
Luke Kenneth Casso... | yield blank so test passes |
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2020-05-25 |
Luke Kenneth Casso... | add stubs |
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2020-05-25 |
Luke Kenneth Casso... | add comments |
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2020-05-25 |
Cesar Strauss | Fix detection of busy_o inside the monitor process |
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2020-05-25 |
Cesar Strauss | Proof of concept of a parallel test |
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2020-05-25 |
Luke Kenneth Casso... | must not do rd-req checking when both imm and zero... |
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2020-05-25 |
Luke Kenneth Casso... | comment out invalid test |
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2020-05-25 |
Luke Kenneth Casso... | lots of greater than 80 chars |
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2020-05-25 |
Luke Kenneth Casso... | switch out req rel if immediate enabled |
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2020-05-25 |
Cesar Strauss | Show oper_r and oper_i in the signal list, in simulation |
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2020-05-24 |
Luke Kenneth Casso... | spelling |
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2020-05-24 |
Luke Kenneth Casso... | spelling |
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2020-05-24 |
Cesar Strauss | Avoid overwriting the first vcd file with the second one |
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2020-05-24 |
Cesar Strauss | Rename the internal DFF of latchregisters to avoid... |
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2020-05-24 |
Luke Kenneth Casso... | move docstring to wiki for compunit |
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2020-05-23 |
Cesar Strauss | Add a few test cases with zero_a set, in combination... |
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2020-05-23 |
Cesar Strauss | Allow zero_a to be set when simulating an operation |
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2020-05-23 |
Luke Kenneth Casso... | common function for op zero and op immed |
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2020-05-23 |
Cesar Strauss | Choose between RA (src1) and zero immediate, conditione... |
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2020-05-23 |
Luke Kenneth Casso... | add comments |
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2020-05-23 |
Luke Kenneth Casso... | split out RegSpecs into separate module |
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2020-05-23 |
Luke Kenneth Casso... | split out RegSpec API into separate class (TODO: move... |
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2020-05-23 |
Luke Kenneth Casso... | add notes on FunctionUnit API |
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2020-05-23 |
Luke Kenneth Casso... | make MultiCompUnit and testing ALU use regspec API... |
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2020-05-23 |
Luke Kenneth Casso... | make demo/test ALU look like nmigen pipeline API |
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2020-05-23 |
Luke Kenneth Casso... | add link to regspecs on wiki |
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2020-05-23 |
Luke Kenneth Casso... | add regspec capability to MultiCompUnit |
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2020-05-23 |
Luke Kenneth Casso... | make immediate-or-RA selection optional based on awaren... |
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2020-05-23 |
Luke Kenneth Casso... | start to morph MultiCompUnit to take "regspec" as the... |
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2020-05-22 |
Luke Kenneth Casso... | update comments for ALUCompUnit |
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2020-05-21 |
Luke Kenneth Casso... | document subkls in CompUnitRecord |
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2020-05-21 |
Luke Kenneth Casso... | code-morph LDSTCompUnit to use RecordObject structure... |
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2020-05-21 |
Cesar Strauss | Fixed typo and left-over from refactoring |
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2020-05-20 |
Luke Kenneth Casso... | convert CompUnit to use CompUnitRecord |
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2020-05-20 |
Luke Kenneth Casso... | fix a series of random imports |
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2020-04-23 |
Luke Kenneth Casso... | comment req_done |
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2020-04-23 |
Luke Kenneth Casso... | hair-raising series of half-way-house changes which... |
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2020-04-23 |
Luke Kenneth Casso... | rename MultiCompUnit |
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