PortInterfaceBase: add dcbz handling
[soc.git] / src / soc / experiment /
2021-10-08 Tobias PlatenPortInterfaceBase: add dcbz handling
2021-10-08 Tobias Platencompldst_multi.py: pass dcbz to portinterface
2021-10-08 Tobias Platentestcase for compldst: wait for address
2021-10-08 Tobias Platenrename ra_needed to zero_a
2021-10-08 Tobias Platenupdate testcase for dcbz
2021-10-08 Tobias Platenadd testcase for dcbz
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-22 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-22 Tobias Platencompldst_multi: add op_is_dcbz signal
2021-09-22 Tobias Platenwhitespace cleanup
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platentestcase: add mmu, link mmu and dcache together
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platencomment out lines that cause test_compldst_multi_mmu...
2021-09-20 Tobias Platenupdate test_compldst_multi_mmu.py
2021-09-19 Cesar StraussReplace "Display" with "print" on simulation process
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-15 isengaaraadd new testcase for ompldst_multi using mmu
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-17 Tobias Platenfix "link addr-go direct to rel"
2021-08-17 Cesar StraussClear operand latch on a terminating condition
2021-08-17 Cesar StraussAdd exc_o.happened to the conditions for terminating...
2021-08-17 Cesar StraussFix activation of cancel signal
2021-08-16 Tobias Platenfix renamed symbols
2021-08-01 Jonathan NeuschäferRename test_dcache, which can't be invoked by test...
2021-07-31 Tobias Platenpartial fix for src/soc/experiment/compldst_multi.py
2021-07-30 Tobias Platenpartially fix unit test in compldst_multi.py
2021-07-26 Tobias Platencompldst_multi: add debug output for dcbz
2021-07-23 Tobias Platentest_dcbz_pi.py: dcbz now working
2021-07-21 Tobias Platentest_dcbz_pi.py: do not use problem state
2021-07-19 Tobias Platentest_dcbz_pi.py: more work on unit test
2021-07-14 Tobias Platenadd more debug outputs, pass dcbz to loadstore/dcache
2021-07-14 Tobias Platendcache: improve debug output
2021-07-11 Tobias Platenmore work on test_dcbz_pi.py
2021-07-11 Tobias Platenimplement pi_dcbz
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-07-11 Tobias Platenadd test_dcbz_pi.py (skeleton only)
2021-07-10 Cesar StraussAdd new traces to the GTKWave document
2021-07-10 Cesar StraussAdd operand producers to the parallel LDST Compunit...
2021-07-10 Cesar StraussDetect unexpected operand fetches and produced results
2021-07-07 Cesar StraussStart of a GTKWave document for the LDST CompUnit paral...
2021-07-04 Cesar StraussBeginning of a class to make a parallel test case for...
2021-06-30 Tobias Platencut down on time by uncommenting data not needed, addin...
2021-06-28 Tobias Platenupdate ldst test case by adding precise timing
2021-06-20 Tobias Platendcache: add debug output
2021-06-20 Tobias Platenupdate test_ldst_pi.py
2021-06-18 Tobias Platenuncomment test_dcache_random
2021-06-14 Tobias Platenupdate testcase for ldst
2021-06-06 Cesar StraussStart a new self-contained test suite for LDSTCompUnit
2021-06-01 Tobias Platentest_ldst_pi.py: add new test case
2021-05-29 Tobias Platentest_ldst_pi.py: first version of test_dcache_random()
2021-05-29 Tobias Platentest_ldst_pi.py: more test_dcache_regression()
2021-05-26 Luke Kenneth Casso... add ldst PortInterface misalign unit test (underway)
2021-05-25 Tobias Platentest_ldst_pi.py: fix race condition causing early stop
2021-05-15 Tobias Platentest_ldst_pi.py: add dcache regression and random test...
2021-05-14 Luke Kenneth Casso... add radix MMU "miss" test
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-14 Luke Kenneth Casso... add misaligned load through MMU (which is incorrectly...
2021-05-13 Luke Kenneth Casso... minor rework of wb_get, make generic
2021-05-13 Luke Kenneth Casso... added STORE test in test_ldst_pi.py, and it worked...
2021-05-13 Luke Kenneth Casso... yet more debug log stuff for DCache, this time on Cache...
2021-05-13 Luke Kenneth Casso... fix wb_get error where data was being corrupted
2021-05-13 Luke Kenneth Casso... add read at different locations in test_ldst_pi.py
2021-05-13 Luke Kenneth Casso... add some data for MMU to actually look up
2021-05-13 Luke Kenneth Casso... ha, hilarious: swapped TLBUpdate output sizes db_out...
2021-05-13 Luke Kenneth Casso... whoops TLBIE must *clear* the valid bit not set it...
2021-05-13 Luke Kenneth Casso... more debug Display in dcache.py
2021-05-13 Luke Kenneth Casso... putting in a lot more debug print statements in DCache...
2021-05-12 Luke Kenneth Casso... add dcache tlb / pte test
2021-05-12 Luke Kenneth Casso... move dcache unit test to separate test_dcache.py
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through...
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-05-12 Luke Kenneth Casso... whoops missing default zero (no idea how)
2021-05-12 Luke Kenneth Casso... addcomments for MMU PortInterface test (how it, um...
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational.
2021-05-12 Luke Kenneth Casso... whitespace
2021-05-12 Luke Kenneth Casso... no need for sel0
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-11 Luke Kenneth Casso... connect MSR.PR to PortInterface in LDSTCompUnit
2021-05-11 Luke Kenneth Casso... add msr_pr bit in PortInterface
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport
2021-05-09 Luke Kenneth Casso... update code-comments
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-05-04 Luke Kenneth Casso... wire in exc_o.happened into write-cancellation of LDSTC...
2021-05-04 Luke Kenneth Casso... comments, and change name of LDSTCompUnit exception_o...
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit
2021-05-02 Luke Kenneth Casso... add nc argument to dcache load/store tests
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic...
2021-05-01 Luke Kenneth Casso... dcache store test: data goes in one cycle AFTER valid...
2021-05-01 Cesar StraussAdd GTKWave documents to each DCache unit test
2021-05-01 Luke Kenneth Casso... whitespace
2021-05-01 Luke Kenneth Casso... missing self.
2021-05-01 Luke Kenneth Casso... resolve DriverConflict in TstL0CacheBuffer, really...
2021-04-26 Luke Kenneth Casso... simple regression dcache test was faulty. wishbone...
2021-04-26 Luke Kenneth Casso... incorrect indentation in dcache rams
2021-04-26 Luke Kenneth Casso... simplify dcache test
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