add MSR reading to issue FSM
[soc.git] / src / soc / experiment /
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... change CSV LD/ST update field to LDSTMode (support...
2020-07-12 Luke Kenneth Casso... update-mode request write signalled too early
2020-07-11 Luke Kenneth Casso... sort out core write latching: gate by busy, and use...
2020-07-11 Luke Kenneth Casso... * clarifying core function unit enable
2020-07-09 Luke Kenneth Casso... munge alu_fsm Shifter into looking like CompALU API...
2020-07-09 Cesar StraussDefine ports for a simple sequential Shifter
2020-07-08 Cesar StraussStart the FSM-based ALU example.
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Cesar StraussClear input data along with valid_i
2020-07-06 Cesar StraussAssert n.ready_i at the beginning of the cycle
2020-07-06 Cesar StraussRemove wait state to demonstrate zero-delay reception.
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussFinally add some well needed comments
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussAdd some wait states in each process
2020-07-06 Cesar StraussNegate inputs after use
2020-07-06 Cesar StraussAdd other tests
2020-07-06 Cesar StraussImplement receiver
2020-07-06 Cesar StraussImplement sender.
2020-07-06 Cesar StraussBegin a new parallel test
2020-07-04 Luke Kenneth Casso... add gitignores
2020-07-02 Luke Kenneth Casso... fix unit tests due to change in using pspec
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-07-02 Cesar StraussPresent the ALU result only when valid_o is active
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
2020-06-28 Cesar StraussAdd missing ports to the test ALU
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... add Config Fetch interface and quick unit test
2020-06-28 Luke Kenneth Casso... add test instruction memory
2020-06-28 Luke Kenneth Casso... add readonly option to TestMemory
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth Casso... new Pi2LSUI working, using PortInterfaceBase
2020-06-28 Luke Kenneth Casso... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth Casso... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... name issue in Pi2LSUI
2020-06-26 Luke Kenneth Casso... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth Casso... correct address in pi2ls
2020-06-26 Luke Kenneth Casso... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth Casso... add in LenExpand shift/mask
2020-06-26 Luke Kenneth Casso... add quick test showing Pi2LSUI not quite reading/writing to
2020-06-26 Luke Kenneth Casso... remove extraneous yields
2020-06-26 Michael NolanModify pi2ls so it passes the portinterface unit tests
2020-06-26 Luke Kenneth Casso... set address ok and fix unit test to check it properly
2020-06-26 Luke Kenneth Casso... add pi.busy_o connection, increase to 64 bit
2020-06-26 Luke Kenneth Casso... unit test broken is ok :)
2020-06-26 Luke Kenneth Casso... set pi.ld.ok to 1 if pi.is_ld_i is set
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... halve the test memory size again
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-25 Luke Kenneth Casso... allow Pi2LSUI to accept incoming PortInterface and...
2020-06-25 Luke Kenneth Casso... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth Casso... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth Casso... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth Casso... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth Casso... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth Casso... annoying error in latest nmigen
2020-06-22 Luke Kenneth Casso... remove unused module
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth Casso... add TestMemoryPortInterface class which is designed...
2020-06-22 Luke Kenneth Casso... comments for LDST CompUnit test
2020-06-22 Luke Kenneth Casso... enable byte-reverse in CompLDSTUnit test
2020-06-22 Luke Kenneth Casso... remove CompLDSTOpSubset, replace with just data_len.
2020-06-22 Luke Kenneth Casso... move BE/LE byte-reverse into LDSTCompUnit
2020-06-19 Luke Kenneth Casso... add TODO comments to upgrade L0CacheBuffer to a new...
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth Casso... add ports to TestMemory
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