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noticed the regular pattern in all pipe_data.py (regspecs).
[soc.git]
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src
/
soc
/
fu
/
compunits
/
test
/
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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commitdiff
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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commitdiff
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
tree
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commitdiff
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
tree
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commitdiff
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
tree
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commitdiff
2020-06-04
Luke Kenneth Casso...
remove unneeded imports
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commitdiff
2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
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commitdiff
2020-06-04
Luke Kenneth Casso...
connect up write-ports from Regfiles to FUs
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commitdiff
2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-06-03
Luke Kenneth Casso...
use common get_cu_inputs for CR unit tests
tree
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commitdiff
2020-06-03
Luke Kenneth Casso...
convert shift_rot tests to use common get_cu_inputs...
tree
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commitdiff
2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-06-03
Luke Kenneth Casso...
reorganise ALU tests, move get_cu_inputs function to...
tree
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commitdiff
2020-06-03
Luke Kenneth Casso...
worked out how to dynamically enable carry-in to ALU...
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commitdiff
2020-06-03
Luke Kenneth Casso...
correct overflow-enable flags for rdmask specs in ALU
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commitdiff
2020-06-03
Luke Kenneth Casso...
attempt to make carry-in and overflow-enable optional...
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commitdiff
2020-06-03
Luke Kenneth Casso...
move over to using power_regspec_map.py from PowerDecod...
tree
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commitdiff
2020-06-03
Luke Kenneth Casso...
move obtaining simulator data into common function...
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commitdiff
2020-06-02
Luke Kenneth Casso...
argh - bad hack, detecting when there are no registers...
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commitdiff
2020-06-02
Luke Kenneth Casso...
take out unneeded code, add Settle() to see if it helps...
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commitdiff
2020-06-02
Luke Kenneth Casso...
hooray, get_cu_inputs now common to both types of tests
tree
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commitdiff
2020-06-02
Luke Kenneth Casso...
remove unneeded variable
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commitdiff
2020-06-02
Luke Kenneth Casso...
decode fast spr for OP_BCREG CTR, TAR and LR
tree
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commitdiff
2020-06-02
Luke Kenneth Casso...
debugging branch fast registers
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commitdiff
2020-06-02
Luke Kenneth Casso...
add read-write register numbering detection
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commitdiff
2020-06-02
Luke Kenneth Casso...
whitespace
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commitdiff
2020-06-02
Luke Kenneth Casso...
rename regspecs to give a consistent naming scheme
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commitdiff
2020-06-01
Luke Kenneth Casso...
remove reading port 3 for CR pipeline. RS moved to...
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commitdiff
2020-06-01
Luke Kenneth Casso...
okaaay add a "rdflags" function which obtains the yes...
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commitdiff
2020-06-01
Luke Kenneth Casso...
RS moved to port 1 (from port 3), remove need in ALU...
tree
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commitdiff
2020-06-01
Luke Kenneth Casso...
argh - need to zero the src_i input after "Read" is...
tree
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commitdiff
2020-06-01
Luke Kenneth Casso...
remove xer so/ov, swap rs/rb to correct(?) order in...
tree
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commitdiff
2020-06-01
Luke Kenneth Casso...
add first version of ShiftRot CompUnit test
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commitdiff
2020-06-01
Luke Kenneth Casso...
add assertions for branch compunit output
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commitdiff
2020-06-01
Luke Kenneth Casso...
decode SPRs for branch
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commitdiff
2020-06-01
Luke Kenneth Casso...
add first version compunit branch test
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commitdiff
2020-06-01
Luke Kenneth Casso...
whoops need to read RS in CR inputs test
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commitdiff
2020-06-01
Luke Kenneth Casso...
add first version of CR CompUnit test
tree
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commitdiff
2020-05-31
Luke Kenneth Casso...
bit-test on the function-unit value being tested
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commitdiff
2020-05-31
Luke Kenneth Casso...
add logical compunit test
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commitdiff
2020-05-31
Luke Kenneth Casso...
comment inputs and outputs from ALU unit test
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commitdiff
2020-05-31
Luke Kenneth Casso...
imports - use of globals. baaaad
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commitdiff
2020-05-31
Luke Kenneth Casso...
remove unneeded code and inputs. convert to "naming...
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commitdiff
2020-05-31
Luke Kenneth Casso...
split out common code from test_alu_compunit.py
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commitdiff
2020-05-31
Luke Kenneth Casso...
de-hard-code-ify getting results from MultiCompUnit
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commitdiff
2020-05-31
Luke Kenneth Casso...
OP_CMP is requesting a change of the output register...
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commitdiff
2020-05-31
Luke Kenneth Casso...
more debug statements
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commitdiff
2020-05-31
Luke Kenneth Casso...
add in more CR debug statements
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commitdiff
2020-05-31
Luke Kenneth Casso...
write cr0 when op.write_cr.ok is set
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commitdiff
2020-05-31
Luke Kenneth Casso...
comment out xer ov/so for now
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commitdiff
2020-05-30
Luke Kenneth Casso...
get carry from cr write_cr
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commitdiff
2020-05-30
Luke Kenneth Casso...
add in write-mask into MultiCompUnit and MCU-ALU unit...
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commitdiff
2020-05-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-05-30
Luke Kenneth Casso...
create read-mask for ALU CompUnit: switches off optiona...
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commitdiff
2020-05-30
Luke Kenneth Casso...
mess - but a functional mess. ALU-MultiCompUnit semi...
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commitdiff
2020-05-30
Luke Kenneth Casso...
grab other results from ALU pipeline in compunit test
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commitdiff
2020-05-30
Luke Kenneth Casso...
order of XER so/ca wrong way round from regspec
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commitdiff
2020-05-29
Luke Kenneth Casso...
trigger read ALU ready/valid from latch as well
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commitdiff
2020-05-28
Luke Kenneth Casso...
extra check on rd.req in test_alu_compunit
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commitdiff
2020-05-28
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-05-28
Luke Kenneth Casso...
debug-print rd/wr rel in test_alu_compunit
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commitdiff
2020-05-28
Luke Kenneth Casso...
debugging test_alu_compunit.py
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commitdiff
2020-05-28
Luke Kenneth Casso...
start on a compunit ALU test
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commitdiff