try to get multi test running
[soc.git] / src / soc / fu /
2021-12-13 Luke Kenneth Casso... convert LoadStore1 to new msr.pr/dr/sf
2021-12-13 Luke Kenneth Casso... add msr to MMU Op Subset record
2021-12-12 Luke Kenneth Casso... delay MMU LOOKUP done by one clock so that the exceptio...
2021-12-12 Luke Kenneth Casso... bring MMU exception out where AllFunctionUnits (and...
2021-12-12 Luke Kenneth Casso... bring exception out from MMU FSM, correct "done"
2021-12-12 Luke Kenneth Casso... add LDSTException output to MMU
2021-12-11 Luke Kenneth Casso... connect up I-Cache to FetchUnitInterface
2021-12-10 Jacob Lifshayadd ternlogi to shift_rot formal test
2021-12-10 Jacob Lifshayfix shift_rot formal proof
2021-12-09 Luke Kenneth Casso... add I-Cache to FSM local variables
2021-12-09 Luke Kenneth Casso... include SPR.TB in SPR FU
2021-12-09 Jacob Lifshayadd bitmanip tests
2021-12-09 Jacob Lifshayadd CommonPipeSpec.__getattr__ to forward attributes...
2021-12-09 Jacob Lifshayadd parent_pspec everywhere
2021-12-09 Jacob Lifshayformat code
2021-12-08 Luke Kenneth Casso... add OP_FETCH_FAILED to MMU Function Unit
2021-12-08 Luke Kenneth Casso... make LoadStore1 intsr_fault a "captured flag" - strictl...
2021-12-08 Luke Kenneth Casso... remove MSR and add CIA to MMU Input Record
2021-12-08 Luke Kenneth Casso... add instr_fault to LoadStore1 FSM
2021-12-08 Jacob Lifshayadd comment about draft instructions
2021-12-08 Jacob Lifshayaccount for Mock absurdities
2021-12-07 Luke Kenneth Casso... set separate "iside" signal in LoadStore1 to not confuse it
2021-12-07 Luke Kenneth Casso... add in I-Cache into LoadStore1 - presently unused ...
2021-12-07 Jacob Lifshaymake bitmanip operations conditional on pspec.draft_bit...
2021-12-07 Jacob Lifshayformat code
2021-12-07 Jacob Lifshaymove rotator mode assignments as requested by lkcl
2021-12-07 Jacob Lifshayformat code
2021-12-05 Luke Kenneth Casso... code-comments
2021-12-05 Luke Kenneth Casso... wishbone bus convert on dcache
2021-12-04 Luke Kenneth Casso... sigh in MMU FSM use direct access to ldst.dar/dsisr...
2021-12-04 Luke Kenneth Casso... put DSISR and DAR publicly accessible in LoadStore1
2021-12-04 Luke Kenneth Casso... whoops fix up exception happened if alignment triggers...
2021-12-04 Luke Kenneth Casso... fixing DAR updating from exceptions
2021-12-04 Luke Kenneth Casso... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-04 Luke Kenneth Casso... store DAR in LoadStore1
2021-12-04 Luke Kenneth Casso... not busy if excrption occurs on MMU_LOOKUP in loadstore.py
2021-12-04 Luke Kenneth Casso... add means to update dsisr from MMU FSM. TODO: add a...
2021-12-03 Luke Kenneth Casso... priv_mode/virt_mode are set in the request, which is...
2021-12-03 Luke Kenneth Casso... in loadstore.py set align_intr from request which comes...
2021-12-03 Luke Kenneth Casso... driver conflict on priv_mode and virt_mode, do not...
2021-12-03 Luke Kenneth Casso... in loadstore.py, when an exception is done or if the FSM
2021-12-03 Luke Kenneth Casso... comment out dsisr and dar in mmu FSM for now
2021-12-02 Jacob Lifshayremove bitmanip fu cuz ternlogi (the only instruction...
2021-12-02 Jacob Lifshayadd ternlogi to shiftrot
2021-12-02 Jacob Lifshayformat code
2021-12-01 Luke Kenneth Casso... stack of changes to MultiCompUnit to speed it up
2021-12-01 Luke Kenneth Casso... experimenting with option to shorten MultiCompUnit...
2021-12-01 Luke Kenneth Casso... create single-stage ALU pipeline, shorten latency on...
2021-12-01 Luke Kenneth Casso... FunctionUnitBaseMulti which derives from ReservationSta...
2021-12-01 Luke Kenneth Casso... use m.submodules[name] instead of getattr
2021-12-01 Luke Kenneth Casso... add Regspecs get_io_spec function
2021-11-30 Luke Kenneth Casso... start allocating more FUs (more ReservationStations)
2021-11-30 Tobias Platenreturn correct data from microwatt
2021-11-30 Tobias Platenloadstore: add done_delay
2021-11-25 Tobias Platenremove unuses dsisr signal
2021-11-25 Tobias Platenreset state to idle on exception
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-19 Luke Kenneth Casso... create lists of latches in each FU, to record the read...
2021-11-17 Jacob Lifshaystart adding bitmanip FU
2021-11-16 Tobias Platenloadstore1 now reports exception reason
2021-11-15 Tobias Platenreport dar on exception + test case
2021-11-10 Luke Kenneth Casso... remove read of MSR, it is done by passing through Power...
2021-11-10 Luke Kenneth Casso... whitespace
2021-11-10 Luke Kenneth Casso... add fetch of MSR in LD/ST pipe_data
2021-11-08 Tobias Platenmmu unit test working again
2021-11-08 Luke Kenneth Casso... remove unneeded imports
2021-11-07 Luke Kenneth Casso... make FSMDivCoreStage properly conform to Stage API
2021-11-07 Luke Kenneth Casso... switch over to single-entry (num_rows=1) ReservationSta...
2021-11-06 Tobias Platenupdate test_issuer_mmu.py testcase, add needed debug...
2021-11-04 Luke Kenneth Casso... use ReservationStations2 (disabled for now)
2021-11-04 Luke Kenneth Casso... fix missing naming ready_i -> i_ready
2021-11-03 Tobias Platencleanup fsm
2021-11-03 Tobias Platenloadstore.py: add Display statement on SPR change
2021-11-03 Tobias Platenadd first tlbie test case
2021-11-02 Tobias Platenmmu fsm: symbols have been renamed
2021-11-02 Tobias Platenhack to fix UnusedElaboratables in src/soc/fu/mmu/test...
2021-11-01 Luke Kenneth Casso... add beginnings of FunctionUnitBaseMulti
2021-11-01 Tobias Platenhack: resolve DriverConflict in src/soc/fu/mmu/fsm.py
2021-10-30 Tobias Platenloadstore.py: add debug output for dcbz
2021-10-10 Luke Kenneth Casso... replace PartitionedSignal with SimdSignal
2021-10-08 Tobias Platenan extra dcbz parameter in all six places
2021-10-08 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-08 Tobias Platendcbz symbol rename
2021-10-08 Tobias Platenloadstore.py: add function set_dcbz_addr
2021-10-03 Tobias Platenan extra dcbz parameter in all six places
2021-10-02 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-02 Tobias Platendcbz symbol rename
2021-10-02 Tobias Platenloadstore.py: add function set_dcbz_addr
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-22 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-22 Jacob Lifshayfix mul fu test helper.py not passing immediate to...
2021-09-22 Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
2021-09-19 Cesar StraussFix rel_o/go_i signal names
2021-09-19 Cesar StraussFix import
2021-09-08 Cesar StraussRemove default argument for dict.get()
2021-09-03 Luke Kenneth Casso... another batch of ready/valid i/o prefix-suffix swaps
2021-08-31 Luke Kenneth Casso... anooother valid_o to convert to o_valid
2021-08-31 Luke Kenneth Casso... update ready/valid in shift_rot test_pipe_caller
2021-08-31 Jacob Lifshayfix test_all_values_covered, missed import when moving...
2021-08-30 Luke Kenneth Casso... update ready/valid i/o_ prefix in div test helper.py
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