shrink test memory size down to only 64 words
[soc.git] / src / soc / fu /
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Luke Kenneth Casso... use while / exception in test_compunit loop
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... use an independent power decoder in ISACaller
2020-06-16 Luke Kenneth Casso... update popcount docstring
2020-06-15 Luke Kenneth Casso... move setup/check memory into helper functions for use...
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily
2020-06-14 Luke Kenneth Casso... add optional LDSTFunctionUnit to compunits
2020-06-14 Luke Kenneth Casso... unit tests showing byte-reverse works
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... update ld/st test to see what is going on
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth Casso... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth Casso... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth Casso... some ugly hacks that get LD/ST immediate working
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-11 Luke Kenneth Casso... must distinguish between rd/write xer_ca sim helpers
2020-06-11 Luke Kenneth Casso... fixing get_rd_sim_xer_ca, has to only read carry if...
2020-06-11 Luke Kenneth Casso... yield needed for unit tests to work (has to go)
2020-06-11 Luke Kenneth Casso... read and write version of get_sim_xer_ca are different
2020-06-11 Luke Kenneth Casso... use ALUHelpers in shift_rot
2020-06-11 Luke Kenneth Casso... add fast spr1/2 sim ALUHelpers
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... link ST.go directly to ST.rel
2020-06-10 Luke Kenneth Casso... add link to bug 361 in FU test
2020-06-10 Luke Kenneth Casso... TODO on RA immediate-zero mode
2020-06-10 Luke Kenneth Casso... re-do cookie-cut of alu test_pipe_caller.py over to...
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output stage of test_pipe_caller
2020-06-10 Luke Kenneth Casso... use sim-get helpers in ALU input fetch
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output phase of test_alu_compunit.py
2020-06-10 Luke Kenneth Casso... continue ALUHelpers check alu outputs code-morph
2020-06-10 Luke Kenneth Casso... code-morph ALU output test check phase
2020-06-10 Luke Kenneth Casso... starting on alu output check
2020-06-10 Luke Kenneth Casso... ilang file output change from alu_pipeline.il to div_pi...
2020-06-10 Luke Kenneth Casso... cookie-cut alu test_pipe_caller.py over
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for ShiftRot test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for Logical test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for CR test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for branch test_pipe_caller.py
2020-06-10 Luke Kenneth Casso... code-munge test_pipe_caller for ALU,
2020-06-10 Jacob Lifshaycreate div pipe setup stage
2020-06-09 Luke Kenneth Casso... correct local variable references
2020-06-09 Luke Kenneth Casso... bit more on TRAP handling (preparing priv instruction)
2020-06-08 Luke Kenneth Casso... add traptype and trapaddr to PowerDecoder2. idea is...
2020-06-08 Luke Kenneth Casso... add traptype and trapaddr to trap_input_data.py
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV...
2020-06-08 Luke Kenneth Casso... set only the SO bit as sticky, not the OV flags as...
2020-06-08 Luke Kenneth Casso... clarify using microwatt calc_ov function.
2020-06-08 Luke Kenneth Casso... added check which shows that OV32 in "adde." is not...
2020-06-08 Luke Kenneth Casso... found section in 3.0B PDF that refers to "Program Inter...
2020-06-08 Luke Kenneth Casso... copy MSR into SRR1 in trap function
2020-06-08 colepoirierFix spelling
2020-06-07 Luke Kenneth Casso... update trap with comments
2020-06-07 colepoirierAdd TrapMainStage.trap() convenience function to set...
2020-06-07 Luke Kenneth Casso... add debug print statements, re-enable all tests in...
2020-06-07 colepoirierAdd back test cases to cookie-cut from for fu/trap...
2020-06-07 Luke Kenneth Casso... add extra tests for mcrf: shows bug is not directly...
2020-06-07 Luke Kenneth Casso... add extra args to ISA in branch test_pipe_caller
2020-06-07 Luke Kenneth Casso... wark-wark, do not & rs[0] into carry-out from rotator
2020-06-07 Luke Kenneth Casso... update rotator.py to match microwatt rotator.vhdl
2020-06-07 Luke Kenneth Casso... add carry test to shift_rot test_pipe_caller: it fails...
2020-06-07 Luke Kenneth Casso... add extra args to ISA in test_pipe_caller.py
2020-06-07 Luke Kenneth Casso... add missing arg to ISA in test_compunit
2020-06-07 Luke Kenneth Casso... add extra missing args to ISA setup in alu test_pipe_caller
2020-06-07 Luke Kenneth Casso... add missing args to ISA
2020-06-07 Luke Kenneth Casso... add MSR to simulator context
2020-06-07 Luke Kenneth Casso... move MSR_PR checking to separate functiong
2020-06-07 colepoirierFix missing 'comb +='
2020-06-06 Luke Kenneth Casso... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth Casso... work out how to initialise memory directly
2020-06-06 Luke Kenneth Casso... initialise L0 Memory from simulator memory
2020-06-06 Luke Kenneth Casso... wait a little for wr.rel to activate if wrmask is active
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... allow Mem in Simulator to be initialised
2020-06-06 Luke Kenneth Casso... use name of unit to write simulator/vcd file
2020-06-06 Luke Kenneth Casso... LDSTCompUnit test data structures linked up, starting...
2020-06-06 Luke Kenneth Casso... set up LDSTCompUnit using regspec
2020-06-06 Luke Kenneth Casso... add special-case LDSTFunctionUnit
2020-06-06 Luke Kenneth Casso... add beginnings of LDST compunit test
2020-06-06 Luke Kenneth Casso... comments / whitespace
2020-06-06 Luke Kenneth Casso... update stage docstring
2020-06-06 Luke Kenneth Casso... code-munge
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-05 colepoirierAdded skeleton fu/trap/test/test_pipe_caller using
2020-06-05 colepoirierAdd trap_input_data.py for fu/trap, cookie-cut from
2020-06-05 Luke Kenneth Casso... update comments
2020-06-05 Luke Kenneth Casso... more comments
2020-06-05 Luke Kenneth Casso... more comments
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