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convert logical to output Data on int reg
[soc.git]
/
src
/
soc
/
fu
/
2020-05-24
Luke Kenneth Casso...
convert logical to output Data on int reg
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commitdiff
2020-05-24
Luke Kenneth Casso...
start using Data in pipelines
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commitdiff
2020-05-24
Luke Kenneth Casso...
cleanup/code-munge on ALU main stage proof
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commitdiff
2020-05-24
Luke Kenneth Casso...
error in alu output stage formal proof setup
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commitdiff
2020-05-24
Luke Kenneth Casso...
output registers need to be Data type (consistently)
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commitdiff
2020-05-24
Luke Kenneth Casso...
spelling mistake in variable
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commitdiff
2020-05-24
Luke Kenneth Casso...
TODO mention OP_MTMSR/OP_MFMSR
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commitdiff
2020-05-24
Luke Kenneth Casso...
add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
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commitdiff
2020-05-23
colepoirier
Added branch and shift_rot imports to fu/compunits...
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commitdiff
2020-05-23
Luke Kenneth Casso...
add input / output stage missing modules
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commitdiff
2020-05-23
Luke Kenneth Casso...
update docs on compunits
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commitdiff
2020-05-23
Luke Kenneth Casso...
remove extraneous test_isel
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commitdiff
2020-05-23
Luke Kenneth Casso...
document purpose of regspec module
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commitdiff
2020-05-23
Luke Kenneth Casso...
split out RegSpecs into separate module
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commitdiff
2020-05-23
Luke Kenneth Casso...
add TODO on multi-in multi-out Function Units
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commitdiff
2020-05-23
Luke Kenneth Casso...
add notes on FunctionUnit API
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commitdiff
2020-05-23
Luke Kenneth Casso...
remove unneeded imports
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commitdiff
2020-05-23
Luke Kenneth Casso...
add link to regspecs on wiki
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commitdiff
2020-05-23
Michael Nolan
Modify proof of isel to use full CR register
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commitdiff
2020-05-23
Michael Nolan
Add test_isel
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commitdiff
2020-05-23
Luke Kenneth Casso...
add CR_ISEL formal proof to CR pipeline
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commitdiff
2020-05-23
Luke Kenneth Casso...
add CR_ISEL (and unit test) to CR pipeline
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commitdiff
2020-05-23
Luke Kenneth Casso...
add gitignore
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commitdiff
2020-05-23
Luke Kenneth Casso...
CR field on Br input data is specd as 0:3 range
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commitdiff
2020-05-23
Luke Kenneth Casso...
add b to CR pipe input data, for isel
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commitdiff
2020-05-22
Luke Kenneth Casso...
add TODO and link to SHIFT_ROT formal bugreport
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove xer.so from ShiftRot formal proof
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove sticky overflow from Shift Rot pipeline
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commitdiff
2020-05-22
Luke Kenneth Casso...
test branch ctr ok flag
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commitdiff
2020-05-22
Luke Kenneth Casso...
cleaner way to test link register ok
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commitdiff
2020-05-22
Luke Kenneth Casso...
whitespace
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commitdiff
2020-05-22
Michael Nolan
Fix link handling in branch proof
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commitdiff
2020-05-22
Luke Kenneth Casso...
variable-name munging for branch formal
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commitdiff
2020-05-22
Michael Nolan
Add formal proof for branch unit, fix bug with bcreg
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commitdiff
2020-05-22
Luke Kenneth Casso...
cleanup logical pipe formal proof
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commitdiff
2020-05-22
Luke Kenneth Casso...
split out Logical Input and Output stages to common...
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commitdiff
2020-05-22
Luke Kenneth Casso...
div probably uses ALU not Logical, needs double-checkin...
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commitdiff
2020-05-22
Luke Kenneth Casso...
soc.fu.logical.input_stage no different from ALU: delete
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commitdiff
2020-05-22
Luke Kenneth Casso...
covert ALU FU to CommonInputStage
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commitdiff
2020-05-22
Luke Kenneth Casso...
create common input pipe spec to avoid code-duplication
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commitdiff
2020-05-22
Luke Kenneth Casso...
move CR over to CompCROpSubset
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commitdiff
2020-05-22
Michael Nolan
Convert branch unit to new CR interface
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commitdiff
2020-05-22
Michael Nolan
Complete CR proof
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove unneeded code
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commitdiff
2020-05-22
Luke Kenneth Casso...
rename ShiftRot to Mul in fu mul test
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commitdiff
2020-05-22
Luke Kenneth Casso...
rename Logical to Div in fu div test
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commitdiff
2020-05-22
Luke Kenneth Casso...
cookie-cut start on div pipe
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commitdiff
2020-05-22
Luke Kenneth Casso...
add cookie-cut mul pipeline template
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commitdiff
2020-05-22
Luke Kenneth Casso...
whitespace
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commitdiff
2020-05-22
Luke Kenneth Casso...
comment tidyup
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commitdiff
2020-05-22
Luke Kenneth Casso...
use CompBROpSubset and reduce it down in size (remove...
tree
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commitdiff
2020-05-22
Luke Kenneth Casso...
code-shuffle
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commitdiff
2020-05-22
Luke Kenneth Casso...
remove accidentally added branch input stage
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commitdiff
2020-05-21
Luke Kenneth Casso...
add fu logical_input_record.py
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commitdiff
2020-05-21
Luke Kenneth Casso...
update CROutputData to use Data()
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commitdiff
2020-05-21
Luke Kenneth Casso...
update comments
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commitdiff
2020-05-21
Luke Kenneth Casso...
whitespace cleanup
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commitdiff
2020-05-21
Luke Kenneth Casso...
whitespace cleanup
tree
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commitdiff
2020-05-21
Luke Kenneth Casso...
remove input_cr, output_cr and is_32bit from CompCROpSubset
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commitdiff
2020-05-21
Luke Kenneth Casso...
add read_cr_whole and write_cr_whole to CompCROpSubset
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commitdiff
2020-05-21
Luke Kenneth Casso...
add first cut at cr_input_record.py
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commitdiff
2020-05-21
Luke Kenneth Casso...
move Logical over to use CompLogicalOpSubset
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commitdiff
2020-05-21
Michael Nolan
Partial attempt at proving the new cr unit.
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commitdiff
2020-05-21
Luke Kenneth Casso...
argh syntax error
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commitdiff
2020-05-21
Luke Kenneth Casso...
update and comment CR Input/Output Data specs
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commitdiff
2020-05-21
Michael Nolan
All CR tests now working
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commitdiff
2020-05-21
Michael Nolan
OP_CROP now working
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commitdiff
2020-05-21
Michael Nolan
Begin porting cr pipeline to new interface
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commitdiff
2020-05-21
Luke Kenneth Casso...
comment CompALUOpSubset, data_len is actually used...
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commitdiff
2020-05-21
Luke Kenneth Casso...
move CompLDSTOpSubset to fu.ldst.ldst_input_record
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commitdiff
2020-05-21
Luke Kenneth Casso...
add zero_a flag to CompALUOpSubset
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commitdiff
2020-05-21
Luke Kenneth Casso...
whitespace/shuffle
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commitdiff
2020-05-21
Luke Kenneth Casso...
move common functionality between PipeSpecs to soc...
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commitdiff
2020-05-21
Luke Kenneth Casso...
move FU IntegerData to directory below
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commitdiff
2020-05-21
Luke Kenneth Casso...
branch output spec nia not cia
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commitdiff
2020-05-21
Luke Kenneth Casso...
add dedicated TrapPipeSpec
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commitdiff
2020-05-21
Luke Kenneth Casso...
create and use ShiftRotPipeSpec
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commitdiff
2020-05-21
Luke Kenneth Casso...
convert to individual PipeSpecs for each pipeline
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commitdiff
2020-05-21
Luke Kenneth Casso...
add regspec to ALUPipeSpec
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commitdiff
2020-05-21
Luke Kenneth Casso...
use branch-specific data structures, add "regspecs...
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commitdiff
2020-05-20
Michael Nolan
Add proof for OP_MCRF
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commitdiff
2020-05-20
Michael Nolan
Add proof for OP_MFCR
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commitdiff
2020-05-20
Michael Nolan
Make test for bpermd exercise the module a bit more
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commitdiff
2020-05-20
Michael Nolan
Revert "*technically* don't use a full crossbar"
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commitdiff
2020-05-20
Luke Kenneth Casso...
add link to bugreport in CR pipe formal test
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commitdiff
2020-05-20
Michael Nolan
*technically* don't use a full crossbar
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commitdiff
2020-05-20
colepoirier
Added OP_BPERMD to fu/logical pipeline, with test
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commitdiff
2020-05-20
Michael Nolan
Revert "assign index to temporary"
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commitdiff
2020-05-20
Michael Nolan
Add proof for OP_CROP
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commitdiff
2020-05-20
Luke Kenneth Casso...
go back to not using LUT in CR pipe
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commitdiff
2020-05-20
Luke Kenneth Casso...
assign index to temporary
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commitdiff
2020-05-20
Luke Kenneth Casso...
store CR lut result in temporary
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commitdiff
2020-05-20
Michael Nolan
Begin adding CR proof
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commitdiff
2020-05-20
Michael Nolan
Fix small bug in op_crop
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commitdiff
2020-05-20
Luke Kenneth Casso...
add register specs to pipeline in/out so that they...
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commitdiff
2020-05-20
Luke Kenneth Casso...
damn. assigning to temporary signals may turn out...
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commitdiff
2020-05-20
Luke Kenneth Casso...
ehn? moo? CR test_pipe_caller locks up 100% CPU on...
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commitdiff
2020-05-20
Luke Kenneth Casso...
correct XER variable names
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commitdiff
2020-05-20
Luke Kenneth Casso...
correct import on shift_rot maskgen
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commitdiff
2020-05-20
Michael Nolan
Use overflow definition from microwatt
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