convert logical to output Data on int reg
[soc.git] / src / soc / fu /
2020-05-24 Luke Kenneth Casso... convert logical to output Data on int reg
2020-05-24 Luke Kenneth Casso... start using Data in pipelines
2020-05-24 Luke Kenneth Casso... cleanup/code-munge on ALU main stage proof
2020-05-24 Luke Kenneth Casso... error in alu output stage formal proof setup
2020-05-24 Luke Kenneth Casso... output registers need to be Data type (consistently)
2020-05-24 Luke Kenneth Casso... spelling mistake in variable
2020-05-24 Luke Kenneth Casso... TODO mention OP_MTMSR/OP_MFMSR
2020-05-24 Luke Kenneth Casso... add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
2020-05-23 colepoirierAdded branch and shift_rot imports to fu/compunits...
2020-05-23 Luke Kenneth Casso... add input / output stage missing modules
2020-05-23 Luke Kenneth Casso... update docs on compunits
2020-05-23 Luke Kenneth Casso... remove extraneous test_isel
2020-05-23 Luke Kenneth Casso... document purpose of regspec module
2020-05-23 Luke Kenneth Casso... split out RegSpecs into separate module
2020-05-23 Luke Kenneth Casso... add TODO on multi-in multi-out Function Units
2020-05-23 Luke Kenneth Casso... add notes on FunctionUnit API
2020-05-23 Luke Kenneth Casso... remove unneeded imports
2020-05-23 Luke Kenneth Casso... add link to regspecs on wiki
2020-05-23 Michael NolanModify proof of isel to use full CR register
2020-05-23 Michael NolanAdd test_isel
2020-05-23 Luke Kenneth Casso... add CR_ISEL formal proof to CR pipeline
2020-05-23 Luke Kenneth Casso... add CR_ISEL (and unit test) to CR pipeline
2020-05-23 Luke Kenneth Casso... add gitignore
2020-05-23 Luke Kenneth Casso... CR field on Br input data is specd as 0:3 range
2020-05-23 Luke Kenneth Casso... add b to CR pipe input data, for isel
2020-05-22 Luke Kenneth Casso... add TODO and link to SHIFT_ROT formal bugreport
2020-05-22 Luke Kenneth Casso... remove xer.so from ShiftRot formal proof
2020-05-22 Luke Kenneth Casso... remove sticky overflow from Shift Rot pipeline
2020-05-22 Luke Kenneth Casso... test branch ctr ok flag
2020-05-22 Luke Kenneth Casso... cleaner way to test link register ok
2020-05-22 Luke Kenneth Casso... whitespace
2020-05-22 Michael NolanFix link handling in branch proof
2020-05-22 Luke Kenneth Casso... variable-name munging for branch formal
2020-05-22 Michael NolanAdd formal proof for branch unit, fix bug with bcreg
2020-05-22 Luke Kenneth Casso... cleanup logical pipe formal proof
2020-05-22 Luke Kenneth Casso... split out Logical Input and Output stages to common...
2020-05-22 Luke Kenneth Casso... div probably uses ALU not Logical, needs double-checkin...
2020-05-22 Luke Kenneth Casso... soc.fu.logical.input_stage no different from ALU: delete
2020-05-22 Luke Kenneth Casso... covert ALU FU to CommonInputStage
2020-05-22 Luke Kenneth Casso... create common input pipe spec to avoid code-duplication
2020-05-22 Luke Kenneth Casso... move CR over to CompCROpSubset
2020-05-22 Michael NolanConvert branch unit to new CR interface
2020-05-22 Michael NolanComplete CR proof
2020-05-22 Luke Kenneth Casso... remove unneeded code
2020-05-22 Luke Kenneth Casso... rename ShiftRot to Mul in fu mul test
2020-05-22 Luke Kenneth Casso... rename Logical to Div in fu div test
2020-05-22 Luke Kenneth Casso... cookie-cut start on div pipe
2020-05-22 Luke Kenneth Casso... add cookie-cut mul pipeline template
2020-05-22 Luke Kenneth Casso... whitespace
2020-05-22 Luke Kenneth Casso... comment tidyup
2020-05-22 Luke Kenneth Casso... use CompBROpSubset and reduce it down in size (remove...
2020-05-22 Luke Kenneth Casso... code-shuffle
2020-05-22 Luke Kenneth Casso... remove accidentally added branch input stage
2020-05-21 Luke Kenneth Casso... add fu logical_input_record.py
2020-05-21 Luke Kenneth Casso... update CROutputData to use Data()
2020-05-21 Luke Kenneth Casso... update comments
2020-05-21 Luke Kenneth Casso... whitespace cleanup
2020-05-21 Luke Kenneth Casso... whitespace cleanup
2020-05-21 Luke Kenneth Casso... remove input_cr, output_cr and is_32bit from CompCROpSubset
2020-05-21 Luke Kenneth Casso... add read_cr_whole and write_cr_whole to CompCROpSubset
2020-05-21 Luke Kenneth Casso... add first cut at cr_input_record.py
2020-05-21 Luke Kenneth Casso... move Logical over to use CompLogicalOpSubset
2020-05-21 Michael NolanPartial attempt at proving the new cr unit.
2020-05-21 Luke Kenneth Casso... argh syntax error
2020-05-21 Luke Kenneth Casso... update and comment CR Input/Output Data specs
2020-05-21 Michael NolanAll CR tests now working
2020-05-21 Michael NolanOP_CROP now working
2020-05-21 Michael NolanBegin porting cr pipeline to new interface
2020-05-21 Luke Kenneth Casso... comment CompALUOpSubset, data_len is actually used...
2020-05-21 Luke Kenneth Casso... move CompLDSTOpSubset to fu.ldst.ldst_input_record
2020-05-21 Luke Kenneth Casso... add zero_a flag to CompALUOpSubset
2020-05-21 Luke Kenneth Casso... whitespace/shuffle
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... move FU IntegerData to directory below
2020-05-21 Luke Kenneth Casso... branch output spec nia not cia
2020-05-21 Luke Kenneth Casso... add dedicated TrapPipeSpec
2020-05-21 Luke Kenneth Casso... create and use ShiftRotPipeSpec
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-21 Luke Kenneth Casso... add regspec to ALUPipeSpec
2020-05-21 Luke Kenneth Casso... use branch-specific data structures, add "regspecs...
2020-05-20 Michael NolanAdd proof for OP_MCRF
2020-05-20 Michael NolanAdd proof for OP_MFCR
2020-05-20 Michael NolanMake test for bpermd exercise the module a bit more
2020-05-20 Michael NolanRevert "*technically* don't use a full crossbar"
2020-05-20 Luke Kenneth Casso... add link to bugreport in CR pipe formal test
2020-05-20 Michael Nolan*technically* don't use a full crossbar
2020-05-20 colepoirierAdded OP_BPERMD to fu/logical pipeline, with test
2020-05-20 Michael NolanRevert "assign index to temporary"
2020-05-20 Michael NolanAdd proof for OP_CROP
2020-05-20 Luke Kenneth Casso... go back to not using LUT in CR pipe
2020-05-20 Luke Kenneth Casso... assign index to temporary
2020-05-20 Luke Kenneth Casso... store CR lut result in temporary
2020-05-20 Michael NolanBegin adding CR proof
2020-05-20 Michael NolanFix small bug in op_crop
2020-05-20 Luke Kenneth Casso... add register specs to pipeline in/out so that they...
2020-05-20 Luke Kenneth Casso... damn. assigning to temporary signals may turn out...
2020-05-20 Luke Kenneth Casso... ehn? moo? CR test_pipe_caller locks up 100% CPU on...
2020-05-20 Luke Kenneth Casso... correct XER variable names
2020-05-20 Luke Kenneth Casso... correct import on shift_rot maskgen
2020-05-20 Michael NolanUse overflow definition from microwatt
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