2021-09-22 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-22 |
Jacob Lifshay | fix mul fu test helper.py not passing immediate to... |
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2021-09-22 |
Luke Kenneth Casso... | alter setup_tst_memory to take a test.mem rather than... |
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2021-09-19 |
Cesar Strauss | Fix rel_o/go_i signal names |
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2021-09-19 |
Cesar Strauss | Fix import |
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2021-09-08 |
Cesar Strauss | Remove default argument for dict.get() |
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2021-09-03 |
Luke Kenneth Casso... | another batch of ready/valid i/o prefix-suffix swaps |
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2021-08-31 |
Luke Kenneth Casso... | anooother valid_o to convert to o_valid |
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2021-08-31 |
Luke Kenneth Casso... | update ready/valid in shift_rot test_pipe_caller |
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2021-08-31 |
Jacob Lifshay | fix test_all_values_covered, missed import when moving... |
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2021-08-30 |
Luke Kenneth Casso... | update ready/valid i/o_ prefix in div test helper.py |
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2021-08-30 |
Luke Kenneth Casso... | fix ready/valid i/o prefix in ALU test |
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2021-08-30 |
Luke Kenneth Casso... | fix CR tests valid/ready naming |
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2021-08-30 |
Luke Kenneth Casso... | missed valid/ready_i/o to o/i_ conversion |
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2021-08-30 |
Luke Kenneth Casso... | missed valid/ready_i/o to o/i_ conversion |
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2021-08-24 |
Luke Kenneth Casso... | replace data_o with o_data and data_i with i_data as... |
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2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
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2021-08-01 |
Jonathan Neuschäfer | soc.simple.test: Rename setup_test_memory to avoid... |
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2021-07-23 |
Tobias Platen | ldst: cleanup debug outputs |
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2021-07-14 |
Luke Kenneth Casso... | update SVSTATE to 64 bit length (fortunately very easy) |
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2021-07-14 |
Tobias Platen | add more debug outputs, pass dcbz to loadstore/dcache |
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2021-07-11 |
Tobias Platen | pass self.pi.is_dcbz to request |
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2021-06-18 |
Tobias Platen | src/soc/fu/ldst/loadstore.py: keep data for the whole... |
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2021-06-10 |
Luke Kenneth Casso... | whoops Popcount datalen too big (wasted bits). reduce |
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2021-05-14 |
Luke Kenneth Casso... | clear out request data on return to idle |
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2021-05-14 |
Luke Kenneth Casso... | sort out LoadStore1 misalignment FSM, also required... |
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2021-05-12 |
Luke Kenneth Casso... | set m_out.load from ldst_r(egister) in LoadStore1 |
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2021-05-12 |
Luke Kenneth Casso... | experimentation with MMU-enabled LoadStore1 through... |
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2021-05-12 |
Luke Kenneth Casso... | add debug info, update comments, disable dcache in... |
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2021-05-12 |
Luke Kenneth Casso... | start doing virtual memory queries via PortInterface... |
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2021-05-11 |
Luke Kenneth Casso... | pass through MSR.PR through PortInterface, into LoadStore1 |
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2021-05-11 |
Luke Kenneth Casso... | add MSR to LD/ST Input Record |
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2021-05-11 |
Luke Kenneth Casso... | comment tidyup |
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2021-05-11 |
Luke Kenneth Casso... | must also pass through instruction fault exception... |
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2021-05-11 |
Luke Kenneth Casso... | whoops names changed in MMU FSM |
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2021-05-11 |
Luke Kenneth Casso... | tidyup comments and remove LoadStore COMPLETE state |
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2021-05-11 |
Luke Kenneth Casso... | cleanup on exception setting |
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2021-05-11 |
Luke Kenneth Casso... | rename LoadStore1 data structures back to microwatt... |
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2021-05-10 |
Luke Kenneth Casso... | add block for MMU activation to LoadStore1 |
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2021-05-10 |
Luke Kenneth Casso... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP... |
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2021-05-10 |
Tobias Platen | style-wise: use ~self.instr_fault not self.instr_fault==0 |
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2021-05-10 |
Tobias Platen | LoadStore1: add rules for MMU_LOOKUP |
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2021-05-09 |
Luke Kenneth Casso... | add comments on translation of MMU_LOOKUP |
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2021-05-09 |
Luke Kenneth Casso... | install MMU_LOOKUP vhdl to be translated to nmigen |
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2021-05-09 |
Luke Kenneth Casso... | move (unused) ACK_WAIT code into FSM |
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2021-05-09 |
Luke Kenneth Casso... | add comments in LoadStore1 |
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2021-05-09 |
Luke Kenneth Casso... | remove invalid setting of d_in.valid from self.mmureq |
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2021-05-09 |
Luke Kenneth Casso... | no SECOND_REQ |
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2021-05-09 |
Luke Kenneth Casso... | remove SECOND_REQ |
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2021-05-09 |
Tobias Platen | src/soc/fu/ldst/loadstore.py drive output d_in.valid |
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2021-05-09 |
Tobias Platen | move skeleton to elaborate |
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2021-05-09 |
Tobias Platen | src/soc/fu/ldst/loadstore.py: add skeleton for fsm |
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2021-05-09 |
Luke Kenneth Casso... | add MMU bugtracker link |
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2021-05-09 |
Luke Kenneth Casso... | update code-comments |
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2021-05-09 |
Luke Kenneth Casso... | add in alignment exception capture/reporting in LoadStore1 |
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2021-05-09 |
Luke Kenneth Casso... | preference is to create a temp variable for comb and... |
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2021-05-09 |
Luke Kenneth Casso... | add misalign flag to PortInterfaceBase |
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2021-05-08 |
Luke Kenneth Casso... | LoadStore1 tidyup |
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2021-05-08 |
Luke Kenneth Casso... | transferring more over to LoadStore FSM |
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2021-05-08 |
Luke Kenneth Casso... | start putting state info into LoadStore1, slowly puttin... |
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2021-05-08 |
Luke Kenneth Casso... | add LoadStore State enum |
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2021-05-08 |
Luke Kenneth Casso... | add bugreport link to mmu |
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2021-05-07 |
Tobias Platen | fix 'sync' referenced before assignment in src/soc... |
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2021-05-07 |
Luke Kenneth Casso... | start setting DSISR bits but commented out |
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2021-05-07 |
Luke Kenneth Casso... | update comments and docstrings |
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2021-05-07 |
Luke Kenneth Casso... | whoops, import error |
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2021-05-07 |
Luke Kenneth Casso... | move LoadStore1 class to soc.fu.ldst.loadstore |
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2021-05-07 |
Luke Kenneth Casso... | whoops was still copying output over in CommonOutputStage |
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2021-05-07 |
Luke Kenneth Casso... | move dsisr and dar into LoadStore1 |
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2021-05-07 |
Luke Kenneth Casso... | move zero-dest-pred in Common Output Stage to not copy... |
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2021-05-06 |
Luke Kenneth Casso... | if zeroing is set, put zero into input or output as... |
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2021-05-05 |
Tobias Platen | fix bug in mmu/fsm.py |
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2021-05-05 |
Luke Kenneth Casso... | put sv_input_record_layout onto CompOpSubsetBase after all |
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2021-05-05 |
Luke Kenneth Casso... | add SVP64 RM fields to ALU input record |
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2021-05-04 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-05-04 |
Tobias Platen | implement MFSPR the same way as fu/spr/main_stage.py |
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2021-05-04 |
Luke Kenneth Casso... | add SVSTATE (SVSRR0) to TRAP pipeline |
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2021-05-04 |
Tobias Platen | upate dsisr and dar using sync |
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2021-05-04 |
Luke Kenneth Casso... | adding fast3 SPR to Trap pipeline and unit test |
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2021-05-04 |
Luke Kenneth Casso... | add printout showing exception output from FUs |
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2021-05-04 |
Luke Kenneth Casso... | more rename of exception_o to exc_o, add convenience... |
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2021-05-04 |
Luke Kenneth Casso... | comments, and change name of LDSTCompUnit exception_o... |
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2021-05-04 |
Luke Kenneth Casso... | remove exception from data on FUBaseData, explicitly... |
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2021-05-04 |
Luke Kenneth Casso... | code-comments for LDSTCompUnit |
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2021-05-04 |
Luke Kenneth Casso... | add LDSTException class to LDSTOutputData |
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2021-05-04 |
Luke Kenneth Casso... | add option to add exception type to FUBaseData (pipe_data) |
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2021-05-04 |
Luke Kenneth Casso... | rename IntegerData to FUBaseData |
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2021-05-04 |
Luke Kenneth Casso... | comment out nc (nocache), it seems to actually work |
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2021-05-03 |
Luke Kenneth Casso... | MMU: get store to activate only when data is available... |
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2021-05-03 |
Luke Kenneth Casso... | disable the cache for now, whilst testing read/write... |
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2021-05-02 |
Luke Kenneth Casso... | use Const to define bit-length when comparing top nibbl... |
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2021-05-02 |
Luke Kenneth Casso... | mmu FSM store in dcache: only put data onto d_in on... |
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2021-05-02 |
Luke Kenneth Casso... | return d_out.valid instead of always "ok" in MMU FSM |
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2021-05-02 |
Luke Kenneth Casso... | HACK WARNING: disable d-cache on hard-coded address... |
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2021-05-01 |
Luke Kenneth Casso... | store data in microwatt dcache goes in one cycle AFTER... |
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2021-05-01 |
Luke Kenneth Casso... | only do dcache lookup for now |
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2021-04-30 |
Luke Kenneth Casso... | debug and stop on mmu test_pipe_caller.py |
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2021-04-30 |
Luke Kenneth Casso... | comments on dcache-to-mmu link |
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2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
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2021-04-30 |
Luke Kenneth Casso... | hook up dcache wb_in/out to PortInterfaceBase Wishbone... |
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