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delay go_st by one cycle, break combinatorial loop
[soc.git]
/
src
/
soc
/
simple
/
issuer_verilog.py
2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-05
Luke Kenneth Casso...
add div FSM as default for test_issuer in verilog and...
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2020-07-30
Luke Kenneth Casso...
ha! have to explicitly specify the ports when writing...
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2020-07-23
Luke Kenneth Casso...
support 32-bit mem width setting
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2020-07-19
Luke Kenneth Casso...
add issuer verilog generator
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projects / soc.git / history