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capture write port (wrflag) in byregfiles_spec for use in
[soc.git]
/
src
/
soc
/
simple
/
test
/
test_microwatt.py
2021-09-25
Las Safin
Merge remote-tracking branch 'upstream/master' into pr
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2021-09-22
Luke Kenneth Casso...
alter setup_tst_memory to take a test.mem rather than...
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2021-08-01
Jonathan Neuschäfer
import setup_i_memory from soc.simple.test.test_runner
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2021-08-01
Jonathan Neuschäfer
soc.simple.test: Rename setup_test_memory to avoid...
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2021-04-23
Luke Kenneth Casso...
use openpower.test.common
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-07-19
Luke Kenneth Casso...
explicitly set up a pc_i_ok signal in test_microwatt.py
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2020-07-11
Luke Kenneth Casso...
more setting bigendian
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2020-07-11
Luke Kenneth Casso...
add bigendian mode to helloworld test
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2020-07-08
Luke Kenneth Casso...
copy binary loaded from disk into data memory as well
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
add hello world binary test
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2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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