Merge branch 'master' of git.libre-soc.org:soc
[soc.git] / src / soc / simple / test /
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working)
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and...
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state,
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-09 Luke Kenneth Casso... add logical test issuer case
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div test cases into test_issuer.py
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayformat some tests
2020-07-26 Luke Kenneth Casso... add nop test cases
2020-07-26 Luke Kenneth Casso... activate some of new accumulator-based tests in test_issuer
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-19 Luke Kenneth Casso... explicitly set up a pc_i_ok signal in test_microwatt.py
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer
2020-07-19 Luke Kenneth Casso... add DivTestCase to test_issuer.py (commented out for...
2020-07-12 Luke Kenneth Casso... add OP_ATTN test back in
2020-07-12 Luke Kenneth Casso... msb of instruction causing sign-overflow
2020-07-11 Luke Kenneth Casso... fix spr setting, set endianness
2020-07-11 Luke Kenneth Casso... more setting bigendian
2020-07-11 Luke Kenneth Casso... add bigendian mode to helloworld test
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth Casso... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth Casso... sorting out setting of XER
2020-07-08 Luke Kenneth Casso... got test_issuer operational on one unit test
2020-07-08 Luke Kenneth Casso... stashing current state of investigation whilst looking...
2020-07-08 Luke Kenneth Casso... copy binary loaded from disk into data memory as well
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... add hello world binary test
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Luke Kenneth Casso... ordering of tests for OP_ATTN needed shuffling. seems...
2020-07-07 Luke Kenneth Casso... debugging termination (OP_ATTN)
2020-07-07 Luke Kenneth Casso... update opcode map for OP_ATTN
2020-07-07 Luke Kenneth Casso... debugging termination / OP_ATTN
2020-07-07 Luke Kenneth Casso... add core start/stop capability, and OP_ATTN support
2020-07-07 Luke Kenneth Casso... add in SPR test cases into test_issuer.py
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... add SPR test case, commented out for now
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... enable general test cases in test_issuer
2020-06-18 Luke Kenneth Casso... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module
2020-06-17 Luke Kenneth Casso... remove unneeded yield
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer
2020-06-16 Luke Kenneth Casso... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth Casso... move debug statements to check function
2020-06-16 Luke Kenneth Casso... move check regs in simple core to separate function
2020-06-16 Luke Kenneth Casso... move test core reg set up into separate function
2020-06-16 Luke Kenneth Casso... add beginnings of TestIssuer class, to issue instructio...
2020-06-16 Luke Kenneth Casso... refer to signals directly in Test Core
2020-06-15 Luke Kenneth Casso... have to set up addr/st rel-go link before setting up...
2020-06-15 Luke Kenneth Casso... add in memory setup/check but disable LDST Unit Tests...
2020-06-08 Luke Kenneth Casso... re-add unit tests back in
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV...
2020-06-08 Luke Kenneth Casso... code-morph test_core for XER bit clarity
2020-06-08 Luke Kenneth Casso... added check which shows that OV32 in "adde." is not...
2020-06-07 Luke Kenneth Casso... assert XER SO/OV/CA registers, check these are ok ...
2020-06-07 Luke Kenneth Casso... add debug print statements, re-enable all tests in...
2020-06-07 Luke Kenneth Casso... add msr to ISA in test_core.py
2020-06-06 Luke Kenneth Casso... missing test.mem arg for ISA in test_core
2020-06-05 Luke Kenneth Casso... comment out CR assertion for now
2020-06-05 Luke Kenneth Casso... experimenting with CR, not quite right
2020-06-04 Luke Kenneth Casso... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth Casso... remove unneeded code
2020-06-04 Luke Kenneth Casso... add branch test case to core
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth Casso... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... add ShiftRot test case (works only because CRs are...
2020-06-04 Luke Kenneth Casso... add both logical and ALU test core
2020-06-04 Luke Kenneth Casso... comment clarify on core
2020-06-04 Luke Kenneth Casso... initialise XER from simulation
next