local variable rename in FetchFSM
[soc.git] / src / soc / simple /
2021-11-22 Luke Kenneth Casso... local variable rename in FetchFSM
2021-11-22 Luke Kenneth Casso... split out FetchFSM into separate module
2021-11-22 Luke Kenneth Casso... whoops accidentally committed commented-out test for...
2021-11-21 Luke Kenneth Casso... reset execute back to ISSUE_START if at INSN_WAIT and
2021-11-21 Luke Kenneth Casso... restrict (refine) hazard selection to the one being...
2021-11-21 Luke Kenneth Casso... block picker hazard on input to PriorityPicker rather...
2021-11-21 Luke Kenneth Casso... parse test_issuer args allow option "allow-overlap...
2021-11-21 Luke Kenneth Casso... complex. TestRunner now does not work properly unless...
2021-11-21 Luke Kenneth Casso... fixed issue with hazard dependencies, read will nott
2021-11-19 Luke Kenneth Casso... add both bitdict and selected args to connect_rd/wrport
2021-11-19 Luke Kenneth Casso... sorting out issue hazard conflicts in core.
2021-11-19 Luke Kenneth Casso... debug and cleanup
2021-11-19 Luke Kenneth Casso... rename instruction_active to instr_active in core
2021-11-19 Luke Kenneth Casso... read latch on regfile ports was fine, the combinatorial...
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-19 Luke Kenneth Casso... latch copy of read register numbers, not in use due...
2021-11-19 Luke Kenneth Casso... use read spec in connect_rdport rather than list of...
2021-11-19 Luke Kenneth Casso... capture write regfile numbers into write latches in...
2021-11-19 Luke Kenneth Casso... code tidyup / comments, and use defaultdict
2021-11-19 Luke Kenneth Casso... create lists of latches in each FU, to record the read...
2021-11-18 Luke Kenneth Casso... remove combinatorial loop in core instruction conflict...
2021-11-18 Luke Kenneth Casso... experimenting with overlapping instructions, bit of...
2021-11-18 Luke Kenneth Casso... set up core processing FSM, which captures data if...
2021-11-18 Luke Kenneth Casso... set up a temporary copy of CoreInput
2021-11-18 Luke Kenneth Casso... experiment allowing overlap (activated with --allow...
2021-11-18 Luke Kenneth Casso... remove unneeded import
2021-11-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-17 Luke Kenneth Casso... reading of regfile bitvector added, which activates...
2021-11-17 Luke Kenneth Casso... add option to test_issuer.py to allow for overlapping...
2021-11-17 Luke Kenneth Casso... add ability to run hazard instruction for test purposes
2021-11-17 Luke Kenneth Casso... detect the case in Core bitvector when the Function...
2021-11-17 Luke Kenneth Casso... missing optional check on make_hazard_vecs
2021-11-17 Luke Kenneth Casso... move core hazard set/clear to separate function, for...
2021-11-17 Luke Kenneth Casso... whoops context-indentation by mistake (no harm done...
2021-11-17 Luke Kenneth Casso... add a FetchOutput pipeline data structure
2021-11-16 Luke Kenneth Casso... print out regfile unary status, bit of name-cleanup
2021-11-16 Luke Kenneth Casso... use a virtual regfile port for the hazard bitvectors
2021-11-16 Luke Kenneth Casso... create set/get ports for bitvectors
2021-11-16 Luke Kenneth Casso... capture write port (wrflag) in byregfiles_spec for...
2021-11-16 Luke Kenneth Casso... rename regports for bitvectors so that
2021-11-16 Luke Kenneth Casso... starting to get write-clear of hazard vectors operating
2021-11-13 Luke Kenneth Casso... start adding hazard vector setting in core (unfinished)
2021-11-11 Luke Kenneth Casso... debug prints
2021-11-11 Luke Kenneth Casso... fix regfile port names for "fast" port access (regreduc...
2021-11-11 Luke Kenneth Casso... code-comments
2021-11-11 Luke Kenneth Casso... split out core input/output into separate file core_data.py
2021-11-11 Luke Kenneth Casso... enable hazard vecs in core
2021-11-11 Luke Kenneth Casso... invert numbering on CR HDLState.get_crregs
2021-11-10 Luke Kenneth Casso... update store data reg 10 to 0xfe in virtmode mmu test
2021-11-10 Luke Kenneth Casso... allow MSR to be set in StateRegs in test_core.py
2021-11-10 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-10 Tobias Platentest testcase for exception
2021-11-10 Luke Kenneth Casso... make core busy_o part of the CoreOutput data structure
2021-11-10 Luke Kenneth Casso... add a "fu_found" signal to core, which allows for an...
2021-11-09 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-09 Tobias Platentest_issuer_mmu.py: add case_5_allsprs
2021-11-09 Luke Kenneth Casso... add core instruction-issue PriorityPickers
2021-11-09 Luke Kenneth Casso... comments
2021-11-09 Luke Kenneth Casso... core.py: create a dictionary of lists of Function Units...
2021-11-09 Luke Kenneth Casso... create function core conect_satellite_decoders
2021-11-08 Luke Kenneth Casso... shorter way of getting FU busy signals
2021-11-08 Luke Kenneth Casso... MultiCompUnit fixed to not need rdmask to be sustained...
2021-11-08 Tobias Platenmmu unit test working again
2021-11-08 Luke Kenneth Casso... remove unused variable
2021-11-08 Luke Kenneth Casso... code comments
2021-11-08 Luke Kenneth Casso... comments
2021-11-08 Luke Kenneth Casso... remove issue_i from core, use i_valid instead to decide...
2021-11-08 Luke Kenneth Casso... move "exception happened" detection from TestIssuer...
2021-11-08 Luke Kenneth Casso... use p.i_valid in core instead of explicit signal ivalid_i
2021-11-08 Luke Kenneth Casso... use Pipeline API o_ready instead of explicit core busy_...
2021-11-08 Luke Kenneth Casso... convert core.py to Pipeline API, deriving from ControlBase
2021-11-08 Luke Kenneth Casso... move simple core input and output data to in/out data...
2021-11-07 Luke Kenneth Casso... for some reason mul test cases had not been added to...
2021-11-06 Tobias Platenupdate test_issuer_mmu.py testcase, add needed debug...
2021-11-05 Tobias Platentlbie, mtspr and mfspr test cases
2021-11-05 Tobias Platenadd mmu/dcache unit test
2021-11-04 Luke Kenneth Casso... add name to write pick on core
2021-11-01 Tobias Platentest_issuer_dcache.py: cleanup
2021-11-01 Luke Kenneth Casso... code comments for core
2021-10-08 klehmancomments for test_runner pr
2021-10-08 klehmanadded comment to teststate
2021-10-08 Luke Kenneth Casso... move TestRunner to openpower-isa now that it is part...
2021-10-08 klehmanadd a state list for method calling
2021-10-08 Luke Kenneth Casso... found accidental commenting-out of memory setup in...
2021-10-08 Luke Kenneth Casso... move debug printout to see whats going on for ldst
2021-10-08 Luke Kenneth Casso... comments
2021-10-08 Luke Kenneth Casso... Revert "move coresync clock synchronisation into HDLRunner"
2021-10-08 Luke Kenneth Casso... call StateRunner constructor, to add to StateRunner...
2021-10-08 Luke Kenneth Casso... more TODO comments
2021-10-08 Luke Kenneth Casso... move coresync clock synchronisation into HDLRunner
2021-10-08 Luke Kenneth Casso... whoops missed one function which should be a yield...
2021-10-08 Luke Kenneth Casso... use yield from on StateRunners
2021-10-08 Luke Kenneth Casso... add comments, remove unneeded code
2021-10-08 Luke Kenneth Casso... move pc_i and svstate_i to HDLRunner
2021-10-08 klehmanadd end_test, minor cleanup, added hdlrun.cleanup(...
2021-10-08 klehmanmoved pc_i and sv_state to constructor, remove hdl_stat...
2021-10-08 klehmanchange over run_hdl_state to TestRunner class
2021-10-08 Luke Kenneth Casso... add dummy call to simrun and end_test()
2021-10-08 Luke Kenneth Casso... code-comments and dummy functions
2021-10-08 Luke Kenneth Casso... move contents of run_sim_state into SimRunner run_test...
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