add in privileged instruction decision-making in PowerDecode2
[soc.git] / src / soc / simulator /
2020-07-13 Luke Kenneth Casso... add simulator test against qemu for extswsli
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... attempting to get test_trap_sim working, seems to switc...
2020-07-12 Luke Kenneth Casso... return unsigned int from binary reading
2020-07-11 Luke Kenneth Casso... sort out big/little endian startup on qemu
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-09 Luke Kenneth Casso... resolving issues with div tests (turned out to be nmuti...
2020-07-09 Luke Kenneth Casso... identifying locations where big/little endian is in...
2020-07-08 Luke Kenneth Casso... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth Casso... switch assembler to little-endian
2020-07-08 Luke Kenneth Casso... add test trap simulator unit test
2020-07-08 Luke Kenneth Casso... allow qemu to stop at specified end point
2020-07-08 Luke Kenneth Casso... add mtspr and bcctrl instructions to helloworld test
2020-07-08 Luke Kenneth Casso... add option to qemu to break at known alternate address
2020-07-08 Luke Kenneth Casso... add code-fragment from microwatt helloworld
2020-07-08 Luke Kenneth Casso... add a simple addis test (regression)
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-07 Luke Kenneth Casso... add ATTN unit test
2020-07-06 Luke Kenneth Casso... whoops forgot that the mul pipeline is actually a pipel...
2020-07-06 Luke Kenneth Casso... continue mul unit test debugging
2020-07-06 Luke Kenneth Casso... improve debug for test_sim.py
2020-07-06 Luke Kenneth Casso... add mullw test to qemu sim
2020-07-06 Luke Kenneth Casso... add first simulator mul test
2020-07-05 Luke Kenneth Casso... fix qemu trap test
2020-06-29 Luke Kenneth Casso... separate out divide by zero cases
2020-06-29 Luke Kenneth Casso... attempting to add overflow setting in ISACaller
2020-06-19 Luke Kenneth Casso... add divide-by-zero test to test_div_sim.py
2020-06-19 Luke Kenneth Casso... add test_0_moduw and correct name to trunc_rem
2020-06-19 Luke Kenneth Casso... add simulator test for divw
2020-06-19 Luke Kenneth Casso... do mix-in for test_sim.py so that jacob can write some...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-18 Luke Kenneth Casso... get instructions immediately from assembly code
2020-06-18 Luke Kenneth Casso... move test_sim.py unit tests to different class (split)
2020-06-17 Luke Kenneth Casso... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth Casso... add loop example, required a bit of munging.
2020-06-14 Luke Kenneth Casso... add sim-qemu test for byte-reversed LD/ST
2020-06-14 Luke Kenneth Casso... add another LD/ST example to qemu-sim test,
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... first cut at qemu memory dump and compare
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Michael Nolanmodify qemu.py to set qemu's cr to 0
2020-06-09 Luke Kenneth Casso... experimenting with CR/LR/XER etc in qemu
2020-06-09 Luke Kenneth Casso... add means to get pc and other qemu registers
2020-06-08 Michael NolanAdd register assertions, fix broken tests
2020-06-08 Michael NolanRestore test_sim.py, begin modifying it for testing...
2020-06-07 Luke Kenneth Casso... add make clean target to qemu_test Makefile
2020-06-02 Michael NolanFix test_bc_reg
2020-05-16 Michael NolanAdd condition.patch
2020-05-07 Luke Kenneth Casso... move unused simulator code out the way
2020-05-04 Tobias Platenupdate cr0 when rc is set
2020-04-20 Tobias Platentestcase fo mulli
2020-04-20 Tobias Platentestcase for addis
2020-04-20 Tobias Platenadd with carry cleanup and test case
2020-04-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-17 Tobias Platenadd with carry instructions
2020-04-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-15 Tobias Platenfix a bug in QemuController.get_register
2020-04-11 Luke Kenneth Casso... add basic comment / docstring on program.py
2020-04-09 Tobias Platenfix 'Object is not an nMigen signal' error in test_sim.py
2020-04-06 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-06 Jacob LifshayMerge branch 'fix-tests'
2020-04-06 Michael NolanAdd test for addpcis
2020-04-06 Jacob Lifshayalmost all tests work
2020-03-26 Luke Kenneth Casso... add TODO for cry_in==CA
2020-03-26 Luke Kenneth Casso... add TODO for cry_in==CA
2020-03-26 Luke Kenneth Casso... fix 1-overflow
2020-03-26 Luke Kenneth Casso... brackets to be safe
2020-03-26 Michael NolanAdd tests for subfic and neg
2020-03-26 Michael NolanSub instruction working
2020-03-26 Luke Kenneth Casso... add newline to stop gnu-as whining
2020-03-26 Luke Kenneth Casso... seeing spurious failures on gdb connection
2020-03-26 Luke Kenneth Casso... wait for communication with closing program and close...
2020-03-25 Michael NolanDirectly compare simulator with qemu
2020-03-25 Michael NolanAssemble whole program instead of instruction by instru...
2020-03-25 Michael NolanAdd rudimentary python qemu interface
2020-03-25 Michael NolanAdd instructions for how to launch qemu
2020-03-25 Michael NolanAdd qemu test directory
2020-03-24 Luke Kenneth Casso... whitespace
2020-03-23 Michael NolanImplement load and store of bytes, halfwords, and words
2020-03-23 Michael NolanAdd support for extended/indexed ld/st
2020-03-23 Michael NolanAdd memory loads and stores to simulator
2020-03-23 Michael NolanBegin adding backend simulator
2020-03-23 Michael NolanMove gnu assembler interface to separate file