move over to from openpower imports
[soc.git] / src / soc / sv / trans / svp64.py
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-03 Cesar StraussDisallow unknown encmodes in SVP64 Assembly
2021-04-02 Cesar StraussPut sanity check inside the existing '2Pred' case,...
2021-04-02 Cesar StraussEnforce explicit src/dest masks on CR twin-predication
2021-04-02 Cesar StraussDisallow mixing of sm=xx and/or dm=xx with m=xx on...
2021-04-02 Cesar StraussDisallow dm=xx on single predication
2021-04-02 Cesar StraussFix typo
2021-04-02 Cesar StraussReally enforce sm=xx not being allowed on single-pred
2021-04-02 Cesar StraussKeep mask mode flags separate
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Luke Kenneth Casso... skip 1-pred check if m= used in SVP64Asm
2021-03-22 Luke Kenneth Casso... read predicate mask from correct point in SVP64Asm
2021-03-22 Luke Kenneth Casso... add SVP64Asm option for "m=" to set both src and dest...
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly
2021-03-20 Luke Kenneth Casso... sort out predicate zeroing in ISACaller
2021-03-20 Luke Kenneth Casso... attempting to add src/dest-zeroing to ISACaller
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-13 Luke Kenneth Casso... add setvl-to-long converter in SVP64Asm (sigh)
2021-03-12 Luke Kenneth Casso... decoding of svp64 reg by name has to occur after immedi...
2021-03-11 Luke Kenneth Casso... add understanding of LDST immediates to SVP64ASM
2021-02-21 Luke Kenneth Casso... add comments for Mode field in SVP64Asm
2021-02-21 Cesar StraussUse symbolic values as field sizes
2021-02-21 Cesar StraussReplace all hardcoded shifts into RM by usage of SVP64R...
2021-02-20 Cesar StraussAssemble the SV64 prefix from its subfields using SVP64...
2021-02-20 Luke Kenneth Casso... fix SVP64Asm Rc=1 assembly
2021-02-16 Cesar StraussFix MSB0 issues for SVP64
2021-02-13 Cesar StraussFix SVP64 translator to yield the unaltered instruction
2021-02-01 Luke Kenneth Casso... construct the assembly-code prefix and base v3.0B in...
2021-01-31 Luke Kenneth Casso... start an ISACaller SVP64 unit test
2021-01-28 Luke Kenneth Casso... move svp64 reg-decode function to more appropriate...
2021-01-27 Luke Kenneth Casso... move SVP64RM CSV class to new module
2021-01-27 Luke Kenneth Casso... also read LDST RM files
2021-01-25 Luke Kenneth Casso... extra comments in svp64
2021-01-24 Luke Kenneth Casso... changing svp64 asm syntax to use / instead of . as... 24jan2021_ls180
2021-01-23 Luke Kenneth Casso... move sanity-checks, add mode into svp64_rm
2021-01-23 Luke Kenneth Casso... cleanup on aisle 3 - simplify sv_mode svp64
2021-01-23 Luke Kenneth Casso... check src/dest mask exist if zeroing, svp64
2021-01-23 Luke Kenneth Casso... add predicate-result svp64 decoding
2021-01-23 Luke Kenneth Casso... add svp64 saturation decoding
2021-01-23 Luke Kenneth Casso... start decoding modes in svp64
2021-01-23 Luke Kenneth Casso... and now for something completely different...
2021-01-23 Luke Kenneth Casso... add elwidth encoding svp64, add more debug-print
2021-01-23 Luke Kenneth Casso... add svp64 subvl encoding
2021-01-23 Luke Kenneth Casso... add in svp64 predicate mask encoding
2021-01-23 Luke Kenneth Casso... capture CR 3 and 5 bit sv encodings
2021-01-23 Luke Kenneth Casso... start decoding EXTRA2/3
2021-01-23 Luke Kenneth Casso... start decoding sv EXTRAs and identifying them
2021-01-23 Luke Kenneth Casso... start to read RM CSV files
2021-01-23 Luke Kenneth Casso... add beginnings of svp64 assembly translator