2020-06-29 |
Luke Kenneth Casso... | first unit test for div |
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2020-06-29 |
Luke Kenneth Casso... | add ignore for parsetab.py |
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2020-06-29 |
Luke Kenneth Casso... | add autogenerated do not commit comment |
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2020-06-29 |
Luke Kenneth Casso... | separate out divide by zero cases |
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2020-06-29 |
Luke Kenneth Casso... | update OV and OV32 ISACaller flags if overflow occurs |
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2020-06-29 |
Luke Kenneth Casso... | attempting to add overflow setting in ISACaller |
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2020-06-29 |
Luke Kenneth Casso... | whoops, hex parser digits are in multiples of 4 bits |
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2020-06-29 |
Luke Kenneth Casso... | fetch instructions from bare wishbone fetch unit |
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2020-06-28 |
Cesar Strauss | Start with a simpler test case |
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2020-06-28 |
Cesar Strauss | Let p.ready_o be active while the test ALU is idle |
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2020-06-28 |
Luke Kenneth Casso... | add cached fetch unit pass-through args |
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2020-06-28 |
Luke Kenneth Casso... | need args to WishboneArbiter, match data width size |
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2020-06-28 |
Cesar Strauss | Add missing ports to the test ALU |
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2020-06-28 |
Luke Kenneth Casso... | read from instruction memory using FetchUnitInterface |
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2020-06-28 |
Luke Kenneth Casso... | add Config Fetch interface and quick unit test |
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2020-06-28 |
Luke Kenneth Casso... | add test instruction memory |
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2020-06-28 |
Luke Kenneth Casso... | add readonly option to TestMemory |
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2020-06-28 |
Luke Kenneth Casso... | expand instruction bus width to 64 bit, start on a... |
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2020-06-28 |
Luke Kenneth Casso... | parameterise minerva i-cache |
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2020-06-28 |
Luke Kenneth Casso... | got Pi2LSUI FSM working |
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2020-06-28 |
Luke Kenneth Casso... | sram address do not cut by LSBs |
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2020-06-28 |
Luke Kenneth Casso... | new Pi2LSUI working, using PortInterfaceBase |
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2020-06-28 |
Luke Kenneth Casso... | start new version of Pi2LSUI based on PortInterfaceBase |
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2020-06-28 |
Luke Kenneth Casso... | pass addr/mask through to PortInterfaceBase rd/wr addr |
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2020-06-28 |
Luke Kenneth Casso... | cleanup (remove unneeded imports) |
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2020-06-28 |
Luke Kenneth Casso... | more code-shuffle for TestMemoryPortInterface |
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2020-06-28 |
Luke Kenneth Casso... | more code-shuffle for TestMemoryPortInterface |
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2020-06-28 |
Luke Kenneth Casso... | minor cleanup, put get/set rdport/wrport into function |
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2020-06-28 |
Luke Kenneth Casso... | merge LDSTPort into TestMemoryPortInterface |
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2020-06-28 |
Luke Kenneth Casso... | use PortInterface connect_port |
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2020-06-28 |
Luke Kenneth Casso... | use PortInterface connect_port |
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2020-06-28 |
Luke Kenneth Casso... | attempt to get Pi2LSUI FSM working |
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2020-06-27 |
Luke Kenneth Casso... | only activate ld_in_progress if addr is ok |
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2020-06-27 |
Luke Kenneth Casso... | make Memory accessible via TestSRAMBareLoadStoreUnit |
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2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
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2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
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2020-06-27 |
Luke Kenneth Casso... | unit test in l0_cache to connect to testpi and test_bare_wb |
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2020-06-27 |
Luke Kenneth Casso... | make PortInterface modules consistent with same API |
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2020-06-27 |
Luke Kenneth Casso... | use ConfigMemoryPortInterface in TstL0CacheBuffer |
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2020-06-27 |
Luke Kenneth Casso... | fix TestMemLoadStoreUnit, it required a FSM to monitor... |
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2020-06-27 |
Luke Kenneth Casso... | add wishbone Pi2LSUI test |
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2020-06-27 |
Luke Kenneth Casso... | reconfigureable PortInterface testing now possible |
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2020-06-26 |
Luke Kenneth Casso... | name issue in Pi2LSUI |
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2020-06-26 |
Luke Kenneth Casso... | whitespace and imports |
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2020-06-26 |
Luke Kenneth Casso... | whitespace |
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2020-06-26 |
Luke Kenneth Casso... | slight reorg on test_pi2ls.py |
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2020-06-26 |
Luke Kenneth Casso... | correct address in pi2ls |
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2020-06-26 |
Luke Kenneth Casso... | oops forgot to initialise base class of TestMemLoadStor... |
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2020-06-26 |
Luke Kenneth Casso... | add in LenExpand shift/mask |
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2020-06-26 |
Luke Kenneth Casso... | add quick test showing Pi2LSUI not quite reading/writing to |
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2020-06-26 |
Luke Kenneth Casso... | remove extraneous yields |
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2020-06-26 |
Michael Nolan | Modify pi2ls so it passes the portinterface unit tests |
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2020-06-26 |
Luke Kenneth Casso... | set address ok and fix unit test to check it properly |
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2020-06-26 |
Luke Kenneth Casso... | add pi.busy_o connection, increase to 64 bit |
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2020-06-26 |
Luke Kenneth Casso... | unit test broken is ok :) |
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2020-06-26 |
Luke Kenneth Casso... | set pi.ld.ok to 1 if pi.is_ld_i is set |
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2020-06-26 |
Michael Nolan | Move tests for pimem to new file, add ability to test... |
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2020-06-26 |
Luke Kenneth Casso... | load/store unit test needed to wait for busy_o |
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2020-06-26 |
Luke Kenneth Casso... | whitespace |
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2020-06-26 |
Luke Kenneth Casso... | clean up output from BareLoadStoreUnit |
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2020-06-26 |
Luke Kenneth Casso... | halve the test memory size again |
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2020-06-26 |
Luke Kenneth Casso... | shrink test memory size down to only 64 words |
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2020-06-26 |
Luke Kenneth Casso... | investigating why write-enable not getting passed through |
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2020-06-26 |
Luke Kenneth Casso... | whoops forgot to call parent elaborate |
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2020-06-26 |
Luke Kenneth Casso... | add test of SRAM through wishbone bus |
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2020-06-26 |
Luke Kenneth Casso... | code-morph which redirects lsmem unit test through... |
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2020-06-26 |
Luke Kenneth Casso... | add a test SRAM that lives behind a minerva LoadStoreUn... |
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2020-06-26 |
Luke Kenneth Casso... | dynamically specify wishbone layout (no longer hardcode... |
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2020-06-26 |
Luke Kenneth Casso... | add reconfigureable Load/Store class |
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2020-06-26 |
Luke Kenneth Casso... | extra parameterification of minerva LoadStoreUnits |
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2020-06-25 |
Luke Kenneth Casso... | allow Pi2LSUI to accept incoming PortInterface and... |
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2020-06-25 |
Luke Kenneth Casso... | add extra parameter, mask_wid, to TestMemLoadStoreUnit |
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2020-06-25 |
Luke Kenneth Casso... | start connecting up Pi2LSUI |
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2020-06-25 |
Luke Kenneth Casso... | add LenExpand module, tidyup on docstring |
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2020-06-25 |
Luke Kenneth Casso... | add beginnings of Pi2LSUI |
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2020-06-25 |
Luke Kenneth Casso... | add attempt at mapping between PortInterface and LoadSt... |
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2020-06-25 |
Luke Kenneth Casso... | rename LoadStoreInterface signals to include _i and... |
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2020-06-25 |
Luke Kenneth Casso... | whitespace |
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2020-06-24 |
Michael Nolan | Revert "modify PortInterface so subfields include the... |
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2020-06-24 |
Michael Nolan | Update comments for LoadStoreUnitInterface |
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2020-06-24 |
Michael Nolan | Have lsmem handle stall and valid signals correctly |
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2020-06-24 |
Michael Nolan | Update comments on LoadStoreUnitInterface again |
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2020-06-24 |
Michael Nolan | Update comments on LoadStoreUnitInterface |
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2020-06-24 |
Michael Nolan | Add handling of byte reads and writes |
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2020-06-24 |
Michael Nolan | Add more complete testbench for lsmem.py |
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2020-06-24 |
Michael Nolan | Super basic first try of testmem with load store unit... |
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2020-06-24 |
Luke Kenneth Casso... | move comments to minerva LoadStoreInterface |
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2020-06-24 |
Luke Kenneth Casso... | import minerva and use LoadStoreUnitInterface |
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2020-06-24 |
Michael Nolan | Add specification for load store interface |
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2020-06-23 |
Michael Nolan | modify PortInterface so subfields include the port... |
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2020-06-23 |
Luke Kenneth Casso... | annoying error in latest nmigen |
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2020-06-23 |
Luke Kenneth Casso... | TstL0CacheBuffer returns array of ports differently now |
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2020-06-22 |
Luke Kenneth Casso... | remove unused module |
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2020-06-22 |
Luke Kenneth Casso... | simplified L0CacheBuffer down to a "PortInterface Arbiter" |
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2020-06-22 |
Luke Kenneth Casso... | add TestMemoryPortInterface class which is designed... |
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2020-06-22 |
Luke Kenneth Casso... | comments for LDST CompUnit test |
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2020-06-22 |
Luke Kenneth Casso... | enable byte-reverse in CompLDSTUnit test |
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2020-06-22 |
Luke Kenneth Casso... | remove CompLDSTOpSubset, replace with just data_len. |
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2020-06-22 |
Luke Kenneth Casso... | move BE/LE byte-reverse into LDSTCompUnit |
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2020-06-20 |
Luke Kenneth Casso... | expand Memory width to 64 and granularity to 16 in... |
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