2020-08-23 |
Luke Kenneth Casso... | add in DMI "stat" loop which monitors core "stopping" |
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2020-08-23 |
Cesar Strauss | Allow an empty style, and passing default styles as... |
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2020-08-23 |
Cesar Strauss | Add comment node type |
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2020-08-23 |
Cesar Strauss | Add base and display styles |
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2020-08-23 |
Cesar Strauss | Apply style from node own name |
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2020-08-23 |
Cesar Strauss | Add color style |
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2020-08-23 |
Cesar Strauss | Collect styles from the tuple |
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2020-08-23 |
Cesar Strauss | Propagate the root style to all signals |
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2020-08-23 |
Luke Kenneth Casso... | comment why litex sim mem map is altered |
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2020-08-23 |
Luke Kenneth Casso... | multiply does not have invert_in, zero_a or invert_out |
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2020-08-22 |
Luke Kenneth Casso... | rename invert_a to invert_in because logical inverts RB |
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2020-08-22 |
Luke Kenneth Casso... | load bios not 1.bin unit test |
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2020-08-22 |
Luke Kenneth Casso... | add extra div regression tests |
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2020-08-22 |
Cesar Strauss | Move comments to the docstring |
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2020-08-22 |
Cesar Strauss | Walk the DOM and emit the trace names |
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2020-08-22 |
Luke Kenneth Casso... | add eqv to logical unit test |
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2020-08-22 |
Luke Kenneth Casso... | add nor and nand to unit test |
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2020-08-22 |
Luke Kenneth Casso... | moved to div pipe temporarily in compunits |
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2020-08-22 |
Luke Kenneth Casso... | bug in andc and orc, complement was taking place on... |
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2020-08-22 |
Luke Kenneth Casso... | extend addis test |
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2020-08-22 |
Luke Kenneth Casso... | add andc and orc tests, failing because RB needs invers... |
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2020-08-22 |
Luke Kenneth Casso... | modsd bug, https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-22 |
Cesar Strauss | First draft of a mini-language to describe GTKWave... |
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2020-08-22 |
Luke Kenneth Casso... | add regression test for nonzero addis |
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2020-08-22 |
Luke Kenneth Casso... | add means to run microwatt test binaries |
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2020-08-22 |
Luke Kenneth Casso... | r0 zero tests on addis, fails |
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2020-08-22 |
Luke Kenneth Casso... | investigating litex sdrinit function |
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2020-08-22 |
Luke Kenneth Casso... | add pseudo-op conversion |
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2020-08-22 |
Luke Kenneth Casso... | add start of litex bios counter loop |
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2020-08-21 |
Luke Kenneth Casso... | remove extraneous comments |
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2020-08-21 |
Luke Kenneth Casso... | testing 64-bit wishbone bus after 32-bit *still* fails... |
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2020-08-21 |
Tobias Platen | typo fix in test_l0_cache_buffer2.py |
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2020-08-21 |
Cole Poirier | dcache.py fix asserts, use backslash and two strings... |
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2020-08-21 |
Cole Poirier | dcache.py replace functions that return signals with... |
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2020-08-21 |
Cole Poirier | wb_types fix typo |
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2020-08-21 |
Tobias Platen | connect TestCachedMemoryPortInterface to LDSTSplitter |
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2020-08-21 |
Luke Kenneth Casso... | get litex sim enabled with 32-bit wishbone bus |
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2020-08-21 |
Luke Kenneth Casso... | ld/st bus reduction test operational |
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2020-08-21 |
Luke Kenneth Casso... | first test of down-converted load/store from 64 to... |
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2020-08-21 |
Luke Kenneth Casso... | first test of down-converted load/store from 64 to... |
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2020-08-21 |
Luke Kenneth Casso... | add in WishboneDownConvert into LoadStoreUnitInterface |
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2020-08-21 |
Luke Kenneth Casso... | comment formatting |
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2020-08-21 |
Luke Kenneth Casso... | remove default values |
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2020-08-21 |
Luke Kenneth Casso... | just range(the_constant) |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline WIP: mullw and mullwu covered. |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline: account for overflow flags. WIP |
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2020-08-21 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-21 |
Cole Poirier | dcache.py commit today and yesterday's progress (sorry... |
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2020-08-21 |
Samuel A. Falvo II | MUL pipeline proofs: mulli / mullw WIP. |
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2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: muldw(u) |
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2020-08-20 |
Samuel A. Falvo II | MUL pipeline proof: signed mulhw |
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2020-08-20 |
Tobias Platen | start wiring TestCachedMemoryPortInterface |
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2020-08-20 |
Tobias Platen | testcase refactoring |
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2020-08-20 |
Tobias Platen | add new class TestCachedMemoryPortInterface |
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2020-08-20 |
Luke Kenneth Casso... | bugfix wishbone downconvert using wb sram 64-to-32... |
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2020-08-20 |
Luke Kenneth Casso... | add a wishbone upconverter |
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2020-08-19 |
Luke Kenneth Casso... | rename and document fields in shift_rot proof |
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2020-08-19 |
Luke Kenneth Casso... | comments in dcache |
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2020-08-19 |
Luke Kenneth Casso... | more subtle interactions between wishbone bus when... |
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2020-08-19 |
Luke Kenneth Casso... | bit of a reorg of mul proof, tracking down missing |
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2020-08-19 |
Luke Kenneth Casso... | move long mul tests to separate unit test |
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2020-08-19 |
Luke Kenneth Casso... | use "Mask" class which is more gate-efficient than... |
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2020-08-19 |
Samuel A. Falvo II | WIP: OP_MUL proofs started. |
tree | commitdiff |
2020-08-19 |
Luke Kenneth Casso... | set up StageChain of 3 mul stages |
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2020-08-18 |
Cole Poirier | fu/mul/test/test_pipe_caller.py test case_all_rb_close_... |
tree | commitdiff |
2020-08-18 |
Tobias Platen | add testcase for LDSTSplitter using PortInterface |
tree | commitdiff |
2020-08-18 |
Luke Kenneth Casso... | fix spr state test |
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2020-08-18 |
Luke Kenneth Casso... | add comment in dcache.py |
tree | commitdiff |
2020-08-17 |
Cole Poirier | dcache.py commit today's progress on translating dcache... |
tree | commitdiff |
2020-08-17 |
Cole Poirier | Create file experiment/wb_types.py to mirror microwatt... |
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2020-08-17 |
Luke Kenneth Casso... | move Mask to nmutil |
tree | commitdiff |
2020-08-17 |
Luke Kenneth Casso... | turn SelectableInt less/greater into signed versions. |
tree | commitdiff |
2020-08-17 |
Luke Kenneth Casso... | use longer memtest in litex sim |
tree | commitdiff |
2020-08-17 |
Luke Kenneth Casso... | adjust litex bios cmp test |
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2020-08-17 |
Luke Kenneth Casso... | fix signed variants of cmp in alu |
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2020-08-17 |
Luke Kenneth Casso... | add new cmp test for alu |
tree | commitdiff |
2020-08-17 |
Luke Kenneth Casso... | use shift module in mmu. to be moved to nmutil |
tree | commitdiff |
2020-08-16 |
Cole Poirier | mmu.py fix formatting 80 char limit |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | attempting to track down bug in litex bios memtest |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | read delay on getting regfile data |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | limit debug reporting in litex sim to range of pc |
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2020-08-16 |
Luke Kenneth Casso... | cmp test from litex bios |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | remove vhdl comments |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | use simple one-line mask-generation |
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2020-08-16 |
Luke Kenneth Casso... | fix LD/ST pimem issue with rising_edge detection |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | missing vars, spelling corrections |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | big reorg, shuffle code to functions, makes the FSM... |
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2020-08-16 |
Luke Kenneth Casso... | spelling error, move perm_ok to local |
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2020-08-16 |
Luke Kenneth Casso... | more comment removal |
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2020-08-16 |
Luke Kenneth Casso... | more remove comments |
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2020-08-16 |
Luke Kenneth Casso... | removing more comments, tidyup |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | restore incorrect removal of zero-Cat at LHS (should... |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | continue tidyup, comment removal/review. use byte_reve... |
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2020-08-16 |
Luke Kenneth Casso... | fix batch of syntax errors found by running mmu.py |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | begin tidyup, removing comments after line-by-line... |
tree | commitdiff |
2020-08-15 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-15 |
Cole Poirier | mmu.py fix Cat() semantics fixes https://bugs.libre... |
tree | commitdiff |
2020-08-15 |
Luke Kenneth Casso... | thanks to daveshah, added simulation of dram |
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2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-15 |
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... |
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