Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 11:56:31 +0000 (11:56 +0000)]
also add blackboxes spblock512* etc.
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 10:54:49 +0000 (10:54 +0000)]
add copying over of spblock*.v and pll.v to build scripts
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 16:30:50 +0000 (16:30 +0000)]
submodule update
Jean-Paul Chaput [Sun, 25 Apr 2021 11:16:57 +0000 (13:16 +0200)]
Correct setup for experiment9/freepdk_c4m45, restrict to 6 metals.
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:47:15 +0000 (20:47 +0000)]
update submodule
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 13:55:14 +0000 (13:55 +0000)]
cleanup mksyms.sh to include FreePDK_C4M45
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 13:53:09 +0000 (13:53 +0000)]
add export of PDKMASTER_TOP to experiments9/freepdk_c4m45
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 13:43:30 +0000 (13:43 +0000)]
correct relative link to FreePDK45_c4m45, use submodule
add note about remembering to run git submodule
Jean-Paul Chaput [Sat, 24 Apr 2021 11:35:30 +0000 (13:35 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Sat, 24 Apr 2021 11:34:35 +0000 (13:34 +0200)]
Forgot to update experiments9 doDesign file for FreePDK 45.
Jean-Paul Chaput [Sat, 24 Apr 2021 11:31:29 +0000 (13:31 +0200)]
Keep in synch with the latest Coriolis. SRAM models in lowercases.
Jean-Paul Chaput [Sat, 24 Apr 2021 11:29:09 +0000 (13:29 +0200)]
Correct settings for experiment10_verilog & FreePDK45.
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:15:07 +0000 (15:15 +0000)]
make placement of SRAMs optional, and PLL as well, in experiment9 freepdk45
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 10:50:52 +0000 (10:50 +0000)]
manually comment out pll and sdcard pins
Staf Verhaegen [Mon, 19 Apr 2021 15:28:20 +0000 (17:28 +0200)]
experiments10_verilog/freepdk_c4m45: Add link for add.py.
Staf Verhaegen [Mon, 19 Apr 2021 14:50:11 +0000 (16:50 +0200)]
Top layer -> metal6
Staf Verhaegen [Tue, 13 Apr 2021 07:39:37 +0000 (09:39 +0200)]
experiments9/freepdk_c4m45: Reduce core size.
With a core size of 1.5x1.5mm the effective space margin is 20%.
Luke Kenneth Casson Leighton [Mon, 19 Apr 2021 18:10:35 +0000 (18:10 +0000)]
add SPBlock512 instance generator
Luke Kenneth Casson Leighton [Mon, 19 Apr 2021 17:38:27 +0000 (17:38 +0000)]
code-comments
Luke Kenneth Casson Leighton [Mon, 19 Apr 2021 17:34:30 +0000 (17:34 +0000)]
add two SRAMs, document how to do more
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 23:30:08 +0000 (23:30 +0000)]
argh, found the blackbox problem: yosys is "doing the right thing" and
identifying spblock as a cell (there are 4 used, therefore it gets identified
as a cell).
also because the blackbox is empty, yosys is optimising it out.
therefore, solution: put something (q = d) into the blackbox, and make
4 each with different names.
yes, it is awful, but it works
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:37:50 +0000 (22:37 +0000)]
try renaming spblock without the underscore
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:34:07 +0000 (22:34 +0000)]
try changing layout of blackbox spblock_512w64b8w
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:51:26 +0000 (20:51 +0000)]
experimenting with blackboxes
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:43:31 +0000 (20:43 +0000)]
rename spblock_512w64b8w, and vco_test_ana for pll
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:20:50 +0000 (20:20 +0000)]
rename blackboxes to lowercase, spblock_512w64b8w, pll
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:19:48 +0000 (20:19 +0000)]
update ls180 sram4k
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 13:51:46 +0000 (13:51 +0000)]
add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst.py complains
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 13:39:42 +0000 (13:39 +0000)]
must use VST_FLAGS uniquify uppercase
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 13:34:22 +0000 (13:34 +0000)]
sort out adding SPBlock_512 SRAM verilog to ls180
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:55:53 +0000 (10:55 +0000)]
update tsmc_018 4k build script
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:53:42 +0000 (10:53 +0000)]
use correct arguments to litex build to create 4k srams sigh
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:30:01 +0000 (10:30 +0000)]
rename ls180sram4k to ls180
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:28:19 +0000 (10:28 +0000)]
add full core variant including 4k sram of ls180
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:27:10 +0000 (10:27 +0000)]
update libresoc.v, c4m-jtag fsm was renamed
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:26:57 +0000 (10:26 +0000)]
update libresoc.v, c4m-jtag fsm was renamed
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:29:22 +0000 (19:29 +0000)]
add an SRAM and wishbone to add test (makes it bigger)
also enable HFNS. this to test cocotb-ghdl
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 10:04:31 +0000 (10:04 +0000)]
connect up boundary scan to inputs/outputs
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 18:52:49 +0000 (18:52 +0000)]
submodule update
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 18:52:42 +0000 (18:52 +0000)]
use METAL10 for topRoutingLayer
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 13:50:45 +0000 (13:50 +0000)]
whoops forgot settings.py
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 22:34:52 +0000 (22:34 +0000)]
submodule update
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 22:34:37 +0000 (22:34 +0000)]
set routingGauge manually
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 18:27:51 +0000 (18:27 +0000)]
enable HFNS in adder
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 18:00:29 +0000 (18:00 +0000)]
include (but do not use) FreePDK45 in experiments10
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:58:07 +0000 (16:58 +0000)]
different FreePDK45 experiments10 chip size
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:44:51 +0000 (16:44 +0000)]
experimentation to get experiment10_verilog work with FreePDK
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:33:21 +0000 (16:33 +0000)]
add FreePDK45 experiments10_verilog doDesign.py
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 16:15:38 +0000 (16:15 +0000)]
add FreePDK45 variant of experiments10_verilog
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 14:06:53 +0000 (14:06 +0000)]
update PLL signal output names
Staf Verhaegen [Mon, 12 Apr 2021 11:24:54 +0000 (13:24 +0200)]
doDesign.py: Disable SRAM placement
Staf Verhaegen [Mon, 12 Apr 2021 11:24:28 +0000 (13:24 +0200)]
Reduce core size.
Using 45nm cells makes the design Pad limited.
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:56:53 +0000 (10:56 +0000)]
rename sys_clk in adder test experiments10_verilog (success compile)
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:54:57 +0000 (10:54 +0000)]
rename JTAG port in adder test experiments10_verilog (success compile)
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:48:42 +0000 (10:48 +0000)]
back to "working" verilog add
Luke Kenneth Casson Leighton [Mon, 12 Apr 2021 10:06:44 +0000 (10:06 +0000)]
another attempt to get 100% completed route
Staf Verhaegen [Mon, 12 Apr 2021 08:02:47 +0000 (10:02 +0200)]
Right branch of c4m-pdk-freedpk45.
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 21:49:46 +0000 (21:49 +0000)]
good grief, increasing ls180 core size to 70,000, 100% route attempt
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 20:09:38 +0000 (20:09 +0000)]
increase core size to see if global routing can be achieved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 20:03:15 +0000 (20:03 +0000)]
whitespace cleanup
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:38:19 +0000 (17:38 +0000)]
use auto-generated pinmux ioPadsSpecs
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:23:18 +0000 (17:23 +0000)]
submodule conflict (update again)
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 17:21:32 +0000 (17:21 +0000)]
use verilog version of ls180 in FreePDK_c4m45
Staf Verhaegen [Sun, 11 Apr 2021 16:14:07 +0000 (18:14 +0200)]
Update c4m-pdk-freepdk45 submodule.
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 16:07:19 +0000 (16:07 +0000)]
crank up the numbers (again)
Staf Verhaegen [Sun, 11 Apr 2021 15:38:45 +0000 (17:38 +0200)]
Wip of P&R of ls180 with C4M FreePDK45.
build_full.sh can run til after `make vst`,
`make lvx` fails.
Staf Verhaegen [Sun, 11 Apr 2021 15:14:13 +0000 (17:14 +0200)]
experiments9: Ignore pinmux generated files.
Staf Verhaegen [Sun, 11 Apr 2021 15:13:47 +0000 (17:13 +0200)]
mksym.sh: Check exitence of alliance-check-toolkit
Staf Verhaegen [Sun, 11 Apr 2021 15:03:50 +0000 (17:03 +0200)]
Submodule for C4M FreePDK45 PDK release files.
Use released-libresoc branch.
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 11:32:15 +0000 (11:32 +0000)]
crank up the numbers to see if routing completion can be achieved
Luke Kenneth Casson Leighton [Sun, 11 Apr 2021 10:43:20 +0000 (10:43 +0000)]
increase katana tracks reserved
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 19:57:45 +0000 (19:57 +0000)]
use verilog for ls180 instead of ilang
Luke Kenneth Casson Leighton [Sat, 10 Apr 2021 11:23:38 +0000 (11:23 +0000)]
make VST names unique, for GHDL to cope
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 16:16:15 +0000 (16:16 +0000)]
sigh, broken experiment10_verilog
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:58:58 +0000 (15:58 +0000)]
whitespace
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:55:38 +0000 (15:55 +0000)]
whitespace cleanup
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 15:55:29 +0000 (15:55 +0000)]
pad name starts with p_
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 12:05:11 +0000 (12:05 +0000)]
rename design of experiments10 to match ls180 chip pads
Luke Kenneth Casson Leighton [Fri, 2 Apr 2021 12:37:38 +0000 (12:37 +0000)]
experiment with nmigen verilog generation
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:41:07 +0000 (22:41 +0000)]
update / refresh full core DFF
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:29:06 +0000 (22:29 +0000)]
update / refresh full core DFF
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:35:18 +0000 (16:35 +0000)]
run doChipFloorplan in experiments10
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:30:45 +0000 (16:30 +0000)]
increase experiment10 JTAG tap width to 4
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 16:04:37 +0000 (16:04 +0000)]
update submodule
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:55:43 +0000 (10:55 +0000)]
update 4k SRAM ls180.il
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 09:45:45 +0000 (09:45 +0000)]
add yosys version number
Jean-Paul Chaput [Mon, 29 Mar 2021 18:54:32 +0000 (20:54 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Mon, 29 Mar 2021 18:53:40 +0000 (20:53 +0200)]
Add a placeholder for the PLL in the doDesign.py for ls180.
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:30:57 +0000 (18:30 +0000)]
Revert "enable high fanout in ls180 experiment9 doDesign.py"
This reverts commit
309301fd58ed12bec149292a40bf1a3c1507d36d.
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:19:23 +0000 (17:19 +0000)]
enable high fanout in ls180 experiment9 doDesign.py
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 07:18:29 +0000 (07:18 +0000)]
aaagh found bug in litex setup, 64 bit WB bus was truncated
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 17:07:22 +0000 (17:07 +0000)]
reduce SPR regfile size considerably
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 14:41:40 +0000 (14:41 +0000)]
reduce INT and FAST regfile sizes by sharing ports
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:27:47 +0000 (20:27 +0000)]
add missing floorplan function call
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 20:27:34 +0000 (20:27 +0000)]
hooray, corrected pinouts
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 17:38:26 +0000 (17:38 +0000)]
really weird error "unsupported direction for eint" which makes no sense
Jean-Paul Chaput [Tue, 23 Mar 2021 19:25:33 +0000 (20:25 +0100)]
Uodated doDesign for the latest ls180 (sram variant).
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:20:45 +0000 (17:20 +0000)]
increase DFF RAM size slightly
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:15:00 +0000 (17:15 +0000)]
add very small DFF srams variant
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 17:08:46 +0000 (17:08 +0000)]
create small dff with 4x 4k SRAMs