soc.git
4 years agouse common TestCase in shift_rot
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:32:56 +0000 (17:32 +0100)]
use common TestCase in shift_rot

4 years agouse common TestCase in alu
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:31:47 +0000 (17:31 +0100)]
use common TestCase in alu

4 years agomove TestCase to common location
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:29:00 +0000 (17:29 +0100)]
move TestCase to common location

4 years agomove reg setup to earlier in test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:28:46 +0000 (17:28 +0100)]
move reg setup to earlier in test

4 years agocomment out wrflag as it should already be in the fu.wr.rel logic
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 15:09:20 +0000 (16:09 +0100)]
comment out wrflag as it should already be in the fu.wr.rel logic

4 years agotest against Logical (hard-coded change)
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:30:44 +0000 (14:30 +0100)]
test against Logical (hard-coded change)

4 years agoadd first cut at test core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:23:26 +0000 (14:23 +0100)]
add first cut at test core

4 years agosync onto fu.go_wr_i otherwise a loop occurs
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:21:42 +0000 (14:21 +0100)]
sync onto fu.go_wr_i otherwise a loop occurs

4 years agoadd rdmask and issue/busy setting
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:06:42 +0000 (14:06 +0100)]
add rdmask and issue/busy setting

4 years agoremove unneeded imports
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:51:01 +0000 (13:51 +0100)]
remove unneeded imports

4 years agouse copy of FHDLTestCase
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:48:17 +0000 (13:48 +0100)]
use copy of FHDLTestCase

4 years agoconnect up write-ports from Regfiles to FUs
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:03:04 +0000 (13:03 +0100)]
connect up write-ports from Regfiles to FUs

4 years agodocstring for AllFunctionUnits
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:54:09 +0000 (12:54 +0100)]
docstring for AllFunctionUnits

4 years agomissing a fastregs write-port
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:53:41 +0000 (12:53 +0100)]
missing a fastregs write-port

4 years agoupdate docstring on simple/core.py
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:31:38 +0000 (12:31 +0100)]
update docstring on simple/core.py

4 years agomove regfile/spec organiser to separate function
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:27:10 +0000 (12:27 +0100)]
move regfile/spec organiser to separate function

4 years agomention convenience variables
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:03:55 +0000 (12:03 +0100)]
mention convenience variables

4 years agorename trap to use convenience variables
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 10:58:49 +0000 (11:58 +0100)]
rename trap to use convenience variables

4 years agoUndo damage done by deleting VHDL microwatt comments,
colepoirier [Thu, 4 Jun 2020 00:22:32 +0000 (17:22 -0700)]
Undo damage done by deleting VHDL microwatt comments,
merge resolution deletion of convenience variables in
fu/trap/main_stage

4 years agocollate fu-enable signals
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:24:20 +0000 (01:24 +0100)]
collate fu-enable signals

4 years agoconnect up Function Unit operand subsets
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:18:34 +0000 (01:18 +0100)]
connect up Function Unit operand subsets

4 years agoforgot to add in rdflag enable
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:55:02 +0000 (00:55 +0100)]
forgot to add in rdflag enable

4 years agowhoops, regfiles are uppercase
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:52:04 +0000 (00:52 +0100)]
whoops, regfiles are uppercase

4 years agowhoops needed a bit of a reorg of the data structure for regfile connections
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:42:44 +0000 (00:42 +0100)]
whoops needed a bit of a reorg of the data structure for regfile connections

4 years agohmmm got naming wrong in regfile-fu connectivity
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:02:35 +0000 (00:02 +0100)]
hmmm got naming wrong in regfile-fu connectivity

4 years agowhoops names of regfiles are lower-case
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 22:46:17 +0000 (23:46 +0100)]
whoops names of regfiles are lower-case

4 years agomunge/redirect the regfile port based on the naming
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 22:28:56 +0000 (23:28 +0100)]
munge/redirect the regfile port based on the naming
"full" ports are the first indexed.
also only enable the read-port enable if the picker is enabled

4 years agoconnect read-enable and src_i to regfile ports
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 22:00:05 +0000 (23:00 +0100)]
connect read-enable and src_i to regfile ports

4 years agolink up PriorityPickers on read channels
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 21:45:12 +0000 (22:45 +0100)]
link up PriorityPickers on read channels

4 years agoput rdspecs into a different dictionary
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 19:22:36 +0000 (20:22 +0100)]
put rdspecs into a different dictionary

4 years agostart putting a non-production core together,
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 19:00:07 +0000 (20:00 +0100)]
start putting a non-production core together,
sorting the read ports first, to get a look at them

4 years agoadd a simple core, not intended for production use
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 17:29:34 +0000 (18:29 +0100)]
add a simple core, not intended for production use

4 years agocorrect comments on regspec decode map
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 14:22:14 +0000 (15:22 +0100)]
correct comments on regspec decode map

4 years agoonly select xer_xo if OE enabled
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:57:48 +0000 (14:57 +0100)]
only select xer_xo if OE enabled

4 years agodecide to elaborate Refiles *into* another class, rather than make them their
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:32:01 +0000 (14:32 +0100)]
decide to elaborate Refiles *into* another class, rather than make them their
own module.  this will reduce a level of hierarchy and make access easier

4 years agoturn RegFiles into module, add all regfiles to it
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:30:00 +0000 (14:30 +0100)]
turn RegFiles into module, add all regfiles to it

4 years agoadd a simple class containing all FunctionUnits
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:18:02 +0000 (14:18 +0100)]
add a simple class containing all FunctionUnits

4 years agomore work on proof_datamerger.py
Tobias Platen [Wed, 3 Jun 2020 13:15:02 +0000 (15:15 +0200)]
more work on proof_datamerger.py

4 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 3 Jun 2020 13:12:01 +0000 (15:12 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

4 years agoadd class containing all regfiles
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 13:07:21 +0000 (14:07 +0100)]
add class containing all regfiles

4 years agowhitespace
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:40:07 +0000 (13:40 +0100)]
whitespace

4 years agouse common get_cu_inputs for CR unit tests
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:35:08 +0000 (13:35 +0100)]
use common get_cu_inputs for CR unit tests

4 years agoconvert shift_rot tests to use common get_cu_inputs function
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:28:24 +0000 (13:28 +0100)]
convert shift_rot tests to use common get_cu_inputs function

4 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 3 Jun 2020 12:19:48 +0000 (14:19 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

4 years agowhitespace fix for proof_datamerger.py
Tobias Platen [Wed, 3 Jun 2020 12:19:40 +0000 (14:19 +0200)]
whitespace fix for proof_datamerger.py

4 years agoreorganise ALU tests, move get_cu_inputs function to common location
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:10:51 +0000 (13:10 +0100)]
reorganise ALU tests, move get_cu_inputs function to common location

4 years agoworked out how to dynamically enable carry-in to ALU: test input_carry against CryIn...
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:52:25 +0000 (12:52 +0100)]
worked out how to dynamically enable carry-in to ALU: test input_carry against CryIn.CA.value

4 years agocorrect overflow-enable flags for rdmask specs in ALU
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:43:25 +0000 (12:43 +0100)]
correct overflow-enable flags for rdmask specs in ALU

4 years agoattempt to make carry-in and overflow-enable optional on ALU
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:41:44 +0000 (12:41 +0100)]
attempt to make carry-in and overflow-enable optional on ALU

4 years agoremove rdflags in pipe_data.py (redundant)
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:31:16 +0000 (12:31 +0100)]
remove rdflags in pipe_data.py (redundant)

4 years agomove over to using power_regspec_map.py from PowerDecode2 rather than distributed...
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:29:02 +0000 (12:29 +0100)]
move over to using power_regspec_map.py from PowerDecode2 rather than distributed maps in pipe_data.py

4 years agomove obtaining simulator data into common function for logical pipe tests
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:10:20 +0000 (12:10 +0100)]
move obtaining simulator data into common function for logical pipe tests

4 years agomention TODO on SPR regfile
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 11:01:37 +0000 (12:01 +0100)]
mention TODO on SPR regfile

4 years agoCheck completion of the sub-processes
Cesar Strauss [Wed, 3 Jun 2020 09:30:04 +0000 (06:30 -0300)]
Check completion of the sub-processes

This detects the case where busy_o goes low before the rel / go
cycle finishes.

4 years agoFixed missing nia.ok.eq(1) in OP_RFID
colepoirier [Wed, 3 Jun 2020 02:27:54 +0000 (19:27 -0700)]
Fixed missing nia.ok.eq(1) in OP_RFID

4 years agoFixed merge conflict by using remote changes
colepoirier [Wed, 3 Jun 2020 02:24:24 +0000 (19:24 -0700)]
Fixed merge conflict by using remote changes

4 years agotidyup branch. comments
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 02:01:50 +0000 (03:01 +0100)]
tidyup branch.  comments

4 years agoconvenience variables
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:55:01 +0000 (02:55 +0100)]
convenience variables

4 years agoFormX not FormXL
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:47:12 +0000 (02:47 +0100)]
FormX not FormXL

4 years agoadd bit more TODO
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:46:58 +0000 (02:46 +0100)]
add bit more TODO

4 years agoupdate submodule for ISA tables
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:39:29 +0000 (02:39 +0100)]
update submodule for ISA tables

4 years agoconvenience rename for spr pipe_data.py, consistent naming for PowerDecode2
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:37:22 +0000 (02:37 +0100)]
convenience rename for spr pipe_data.py, consistent naming for PowerDecode2

4 years agoSimplify immediate check
Cesar Strauss [Wed, 3 Jun 2020 01:28:56 +0000 (22:28 -0300)]
Simplify immediate check

4 years agoadd more TODOs
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:26:58 +0000 (02:26 +0100)]
add more TODOs

4 years agoPreliminary check of the alu protocol
Cesar Strauss [Wed, 3 Jun 2020 01:16:07 +0000 (22:16 -0300)]
Preliminary check of the alu protocol

Still need to check that the operand to the alu is held stable.
For now, it's more like a placeholder of what will become the full check.

4 years agoPass along the operand, in the cycle in which go is active
Cesar Strauss [Wed, 3 Jun 2020 01:07:33 +0000 (22:07 -0300)]
Pass along the operand, in the cycle in which go is active

4 years agoFixed OP_RFID and OP_SC in fu/trap/main_stage
colepoirier [Wed, 3 Jun 2020 01:11:02 +0000 (18:11 -0700)]
Fixed OP_RFID and OP_SC in fu/trap/main_stage

4 years agoadd some more constants and ref to POWER9 pdf
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 00:58:36 +0000 (01:58 +0100)]
add some more constants and ref to POWER9 pdf

4 years agoadd an if for OP_MTMSR and some comments
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 00:45:33 +0000 (01:45 +0100)]
add an if for OP_MTMSR and some comments

4 years agoAttempted to fix OP_RFID in TRAP pipeline
colepoirier [Wed, 3 Jun 2020 00:07:39 +0000 (17:07 -0700)]
Attempted to fix OP_RFID in TRAP pipeline

4 years agoImplement TRAP instructions OP_RFID and OP_SC
colepoirier [Tue, 2 Jun 2020 23:41:37 +0000 (16:41 -0700)]
Implement TRAP instructions OP_RFID and OP_SC

4 years agoargh - bad hack, detecting when there are no registers to write, in MultiCompUnit
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 22:39:43 +0000 (23:39 +0100)]
argh - bad hack, detecting when there are no registers to write, in MultiCompUnit

4 years agotake out unneeded code, add Settle() to see if it helps with bug
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:59:34 +0000 (22:59 +0100)]
take out unneeded code, add Settle() to see if it helps with bug

4 years agoadd lk field to DecodeOut2
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:52:14 +0000 (22:52 +0100)]
add lk field to DecodeOut2

4 years agomove setting cia input to branch from get_cu_inputs function
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:07:46 +0000 (22:07 +0100)]
move setting cia input to branch from get_cu_inputs function

4 years agohooray, get_cu_inputs now common to both types of tests
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:07:25 +0000 (22:07 +0100)]
hooray, get_cu_inputs now common to both types of tests

4 years agooooo very annoying. there does not appear to be any difference between two set_input...
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:57:28 +0000 (21:57 +0100)]
oooo very annoying.  there does not appear to be any difference between two set_inputs functions

4 years agoadd get_inputs function to branch test_pipe_caller
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:36:11 +0000 (21:36 +0100)]
add get_inputs function to branch test_pipe_caller

4 years agoremove unneeded variable
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:35:54 +0000 (21:35 +0100)]
remove unneeded variable

4 years agoRevert "ok ok - for OP_BCREG put CTR in spr2 as well"
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:28:01 +0000 (21:28 +0100)]
Revert "ok ok - for OP_BCREG put CTR in spr2 as well"

This reverts commit 87810631b7ecbd34ad89b2853bbdb763fe003633.

4 years agook ok - for OP_BCREG put CTR in spr2 as well
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:25:50 +0000 (21:25 +0100)]
ok ok - for OP_BCREG put CTR in spr2 as well

4 years agoSelect spr1 for bcctr - use fast_spr decoding from decoder
Michael Nolan [Tue, 2 Jun 2020 20:23:28 +0000 (16:23 -0400)]
Select spr1 for bcctr - use fast_spr decoding from decoder

4 years agoset up CTR and LR only on BCREG when needed
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:18:53 +0000 (21:18 +0100)]
set up CTR and LR only on BCREG when needed

4 years agodecode fast spr for OP_BCREG CTR, TAR and LR
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:15:35 +0000 (21:15 +0100)]
decode fast spr for OP_BCREG CTR, TAR and LR

4 years agoadd TODO comments for read_fast1/2
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 19:15:50 +0000 (20:15 +0100)]
add TODO comments for read_fast1/2

4 years agoproof_datamerger: proof that output is zero when idle
Tobias Platen [Tue, 2 Jun 2020 19:13:35 +0000 (21:13 +0200)]
proof_datamerger: proof that output is zero when idle

4 years agoargh overlapping commits on submodule (rebase did not work properly)
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 19:01:38 +0000 (20:01 +0100)]
argh overlapping commits on submodule (rebase did not work properly)
extra commit just to make sure it updates properly

4 years agodebugging branch fast registers
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 18:59:34 +0000 (19:59 +0100)]
debugging branch fast registers

4 years agoFix broken wiki version
Michael Nolan [Tue, 2 Jun 2020 18:42:29 +0000 (14:42 -0400)]
Fix broken wiki version

4 years agoHandle removal of spr2 field from decoder
Michael Nolan [Tue, 2 Jun 2020 18:27:40 +0000 (14:27 -0400)]
Handle removal of spr2 field from decoder

4 years agoadd comment about fast1 and fast2 in branch test_pipe_caller
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 18:26:11 +0000 (19:26 +0100)]
add comment about fast1 and fast2 in branch test_pipe_caller

4 years agoadd regspecmap function to PowerDecode2
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 18:20:52 +0000 (19:20 +0100)]
add regspecmap function to PowerDecode2

4 years agoFix test_bc_reg
Michael Nolan [Tue, 2 Jun 2020 18:10:45 +0000 (14:10 -0400)]
Fix test_bc_reg

4 years agoFix issues with test_bc_reg, wrong instruction field for CR selector
Michael Nolan [Tue, 2 Jun 2020 17:20:23 +0000 (13:20 -0400)]
Fix issues with test_bc_reg, wrong instruction field for CR selector

4 years agomove regspec function to separate module
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 17:39:35 +0000 (18:39 +0100)]
move regspec function to separate module

4 years agoadd in fast regs support in decoder and into regspec_decode
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 17:34:29 +0000 (18:34 +0100)]
add in fast regs support in decoder and into regspec_decode

4 years agoadd 2nd write-reg for LD/ST Update mode
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 17:02:11 +0000 (18:02 +0100)]
add 2nd write-reg for LD/ST Update mode

4 years agoadd write-regs encoding to regspec decoder
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:52:42 +0000 (17:52 +0100)]
add write-regs encoding to regspec decoder

4 years agoadd read-write register numbering detection
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:32:12 +0000 (17:32 +0100)]
add read-write register numbering detection

4 years agowhoops cut/paste error, creating write_ports not read_ports
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:15:16 +0000 (17:15 +0100)]
whoops cut/paste error, creating write_ports not read_ports