Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:31:32 +0000 (00:31 +0000)]
remove blackbox attribute on SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Sat, 6 Mar 2021 00:28:49 +0000 (00:28 +0000)]
add SPBlock_512W64B8W.v blackbox file
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 23:11:11 +0000 (23:11 +0000)]
remove sram4k wishbone bte/cti in litex interconnect
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 21:08:28 +0000 (21:08 +0000)]
litex expects wishbone "err" signals even if not used
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 19:14:53 +0000 (19:14 +0000)]
extend name of sram4k block with _wb suffix
Tobias Platen [Fri, 5 Mar 2021 16:47:53 +0000 (17:47 +0100)]
unit test: pass bool mmu
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 16:33:05 +0000 (16:33 +0000)]
add comments and more stub functions
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 16:16:41 +0000 (16:16 +0000)]
add segment_check function, plus quick test.
also fix order because SelectableInt deals in BE
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 14:20:21 +0000 (14:20 +0000)]
add decode_prte function to RADIX
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 13:53:47 +0000 (13:53 +0000)]
add trivial LD/ST redirectors into RADIX ISACaller
Cesar Strauss [Fri, 5 Mar 2021 12:01:34 +0000 (09:01 -0300)]
Move writing of the PC state register to the issue FSM
Before fetch, update the PC state register with the NIA, unless PC was
modified in execute.
Cesar Strauss [Fri, 5 Mar 2021 10:57:01 +0000 (07:57 -0300)]
Move the wait on "core stop" out of fetch, and into issue
During a Simple-V loop, the fetch FSM will sit idle, unable to pause the
execution. A good alternate place to wait on "core stop" release is at
instruction end, before either fetching a new instruction, or going back
to the SV loop.
On system initialization, we need to pause as well, since there was no
instruction which ended previously.
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 21:32:59 +0000 (21:32 +0000)]
removing --user from make develop
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 21:26:47 +0000 (21:26 +0000)]
whitespace
Tobias Platen [Thu, 4 Mar 2021 19:16:50 +0000 (20:16 +0100)]
update test_caller_radix.py
Tobias Platen [Thu, 4 Mar 2021 19:05:44 +0000 (20:05 +0100)]
ISACaller: add option mmu
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:15:40 +0000 (18:15 +0000)]
whoops microwatt already allocates SPR 720
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 18:06:57 +0000 (18:06 +0000)]
add comments from gem5-experimental mmu
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:47:21 +0000 (17:47 +0000)]
add cached pgtbl0/3
Luke Kenneth Casson Leighton [Thu, 4 Mar 2021 17:39:53 +0000 (17:39 +0000)]
add two functions for checking permissions, to be based on microwatt
Tobias Platen [Wed, 3 Mar 2021 18:23:01 +0000 (19:23 +0100)]
add RADIX skeleton and unit test
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:45:55 +0000 (17:45 +0000)]
add debug strings
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 17:07:00 +0000 (17:07 +0000)]
remove singleton pattern
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 16:13:43 +0000 (16:13 +0000)]
add pywriter Makefile entry
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:28:53 +0000 (14:28 +0000)]
cur_state is a global, does not have to be passed as a parameter in TestIssuer
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:18:46 +0000 (14:18 +0000)]
set SVSTATE in TestRunner using new TestIssuer.svstate_i
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 14:15:18 +0000 (14:15 +0000)]
add svstate_i to TestIssuer which mirrors pc_i
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:32:20 +0000 (16:32 +0000)]
comment out changing SPR 720 because 720 is not supported by the MMU pipe
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 16:24:50 +0000 (16:24 +0000)]
sort out SPR setting in MMU
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 13:55:17 +0000 (13:55 +0000)]
operating correctly, not directing MMU SPRs to SPR Pipeline,
failure with PC likely due to ISACaller not supporting SPR 720
Luke Kenneth Casson Leighton [Tue, 2 Mar 2021 12:49:18 +0000 (12:49 +0000)]
must always set ok for writing out data otherwise it never hits regfile
(and causes compunit to fail)
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 19:35:31 +0000 (19:35 +0000)]
Revert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2"
This reverts commit
0b31706069567c4124ebac487f238342cc540d79.
Luke Kenneth Casson Leighton [Mon, 1 Mar 2021 15:40:31 +0000 (15:40 +0000)]
move SVP64 RM decoder to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 18:36:22 +0000 (18:36 +0000)]
add additional SVP64 RM decode fields
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 17:19:18 +0000 (17:19 +0000)]
start on SVP64 RM Mode decoder
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:29:54 +0000 (16:29 +0000)]
more SVP64 enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 16:21:42 +0000 (16:21 +0000)]
add SVP64 RM sub-field enums
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:47:25 +0000 (14:47 +0000)]
move SVP64 Extra decoders to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:43:09 +0000 (14:43 +0000)]
fix syntax error
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:35 +0000 (14:42 +0000)]
move SVP64PrefixDecoder to separate module
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 14:42:12 +0000 (14:42 +0000)]
add PowerDecoder.no_in_vec
Luke Kenneth Casson Leighton [Sun, 28 Feb 2021 12:19:52 +0000 (12:19 +0000)]
add svp64_instrs to power_svp64
Tobias Platen [Sun, 28 Feb 2021 11:25:51 +0000 (12:25 +0100)]
fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2
Tobias Platen [Sun, 28 Feb 2021 11:14:31 +0000 (12:14 +0100)]
fix Bug 603 - use SPR names/numbers from sprs.csv
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:43:35 +0000 (12:43 +0000)]
use PowerDecoder2.no_out_vec instead of manual vector detection in ISACaller
Luke Kenneth Casson Leighton [Sat, 27 Feb 2021 12:38:15 +0000 (12:38 +0000)]
add corresponding VL=0 unit test as from
161b7d67b in svp64_cases.py
Cesar Strauss [Sat, 27 Feb 2021 09:25:47 +0000 (06:25 -0300)]
Add traces for the new FSM
Cesar Strauss [Fri, 26 Feb 2021 21:45:18 +0000 (18:45 -0300)]
Add a vector case with VL == 0
This will be useful for testing the fetch <-> issue loop.
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:50:04 +0000 (13:50 +0000)]
comment on CoreState
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:46:22 +0000 (13:46 +0000)]
remove sv_changed input to fetch_fsm, add it to issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:40:22 +0000 (13:40 +0000)]
moving new_svstate and update_svstate into issue FSM TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:34:59 +0000 (13:34 +0000)]
move fetch_insn_o into issue_fsm TestIssuer
Luke Kenneth Casson Leighton [Fri, 26 Feb 2021 13:21:31 +0000 (13:21 +0000)]
add comments, missing that VL loop ends after execution if no_out_vec set
SVP64 TestIssuer
Cesar Strauss [Fri, 26 Feb 2021 10:47:03 +0000 (07:47 -0300)]
Implement a decode/issue FSM between fetch and execute
The idea is for it to:
* keep looping "fetch" while VL==0 on a vector instruction.
* keep looping "execute" while SRCSTEP != VL-1.
* unless PC/SVSTATE was modified by "execute", in that case do go back
to "fetch".
* update PC and SRCSTEP accordingly.
Tobias Platen [Wed, 24 Feb 2021 18:43:23 +0000 (19:43 +0100)]
wb_get: write outputs to seperate logfile too
Tobias Platen [Wed, 24 Feb 2021 18:40:53 +0000 (19:40 +0100)]
update mmu testcase
Tobias Platen [Wed, 24 Feb 2021 18:39:59 +0000 (19:39 +0100)]
test_runner.py: add needed imports
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:22:20 +0000 (15:22 +0000)]
add comments explaining split
https://bugs.libre-soc.org/show_bug.cgi?id=606
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:19:16 +0000 (15:19 +0000)]
move DecodeCROut/In (at last) out of PowerDecoderSubset and into PowerDecoder2
https://bugs.libre-soc.org/show_bug.cgi?id=606
Luke Kenneth Casson Leighton [Wed, 24 Feb 2021 15:08:32 +0000 (15:08 +0000)]
start making write_cr0 independent of DecodeCROut
https://bugs.libre-soc.org/show_bug.cgi?id=606
Tobias Platen [Tue, 23 Feb 2021 18:20:15 +0000 (19:20 +0100)]
deduplicate
Luke Kenneth Casson Leighton [Tue, 23 Feb 2021 13:43:35 +0000 (13:43 +0000)]
add note that SVSTATE has changed, this will allow picking up that
Trap pipeline has altered SVSTATE
Cesar Strauss [Mon, 22 Feb 2021 21:29:11 +0000 (18:29 -0300)]
Fix typo when calculating PowerDecoder2.no_out_vec
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:21:26 +0000 (16:21 +0000)]
move setting of NIA into fetch FSM in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:00:24 +0000 (16:00 +0000)]
whoops
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 15:59:33 +0000 (15:59 +0000)]
moving PC-setting (NIA) out of execute_fsm in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 14:48:46 +0000 (14:48 +0000)]
rename inter-FSM handshake signals in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:27:06 +0000 (19:27 +0000)]
err trying to put in some FSM handshake signals, getting confused
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:38 +0000 (19:20 +0000)]
comment for where SVSTATE FSM should go
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:17 +0000 (19:20 +0000)]
add CR out vector detection to PowerDecoder2 no_out_vec
Cesar Strauss [Sun, 21 Feb 2021 17:21:54 +0000 (14:21 -0300)]
The field selection function was moved to nmutil.util
All previous users were updated.
Cesar Strauss [Sun, 21 Feb 2021 17:18:15 +0000 (14:18 -0300)]
Hide the register augmentation traces by default
This saves some vertical space if you are not interested in seeing this
level of detail, but it is still there if you need it.
Needs the latest nmutil version for it to work.
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:50:31 +0000 (15:50 +0000)]
move execute_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:41:08 +0000 (15:41 +0000)]
move fetch_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:22:28 +0000 (15:22 +0000)]
add JTAG enable/disable of 4k SRAMs
Cesar Strauss [Sun, 21 Feb 2021 14:50:21 +0000 (11:50 -0300)]
The new version of "sel" is smart enough to find a suitable Signal name
An up-to-date version of nmutil is required for this.
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 13:08:32 +0000 (13:08 +0000)]
add comments for Mode field in SVP64Asm
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 12:58:19 +0000 (12:58 +0000)]
comments in SVP64RMFields
Cesar Strauss [Sun, 21 Feb 2021 12:54:20 +0000 (09:54 -0300)]
Use the new selection field function from nmutil
Note that the new function accepts a Module on which it to generate its
wires, and returns a Signal of the appropriate size.
Be sure to update nmutil to get the new function.
Cesar Strauss [Sun, 21 Feb 2021 09:58:54 +0000 (06:58 -0300)]
Use symbolic values as field sizes
Cesar Strauss [Sat, 20 Feb 2021 23:00:02 +0000 (20:00 -0300)]
Replace all hardcoded shifts into RM by usage of SVP64RMFields
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 01:04:50 +0000 (01:04 +0000)]
create SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:38:17 +0000 (23:38 +0000)]
comments on sv.add. Rc=1 unit test
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:32:50 +0000 (23:32 +0000)]
add in Vectorised CRs when Rc=1 into ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:15:06 +0000 (23:15 +0000)]
add CR1 to DecodeCRIn/Out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 22:13:20 +0000 (22:13 +0000)]
add some debug checking to get_pdecode_cr_out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:55:57 +0000 (21:55 +0000)]
add crossreference to bug #603
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:44:48 +0000 (21:44 +0000)]
add more debug output to get_pdecode_cr_out
Cesar Strauss [Sat, 20 Feb 2021 21:12:03 +0000 (18:12 -0300)]
Actually forward the field width to field_slice()
This means that field extraction of multi-bit subfields, for field sizes
other than 64 bits, was buggy up to now.
Fortunately, there were no users of non-default field sizes so far.
Cesar Strauss [Sat, 20 Feb 2021 20:09:42 +0000 (17:09 -0300)]
Assemble the SV64 prefix from its subfields using SVP64PrefixFields
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:26 +0000 (20:49 +0000)]
start on CRs in SVP64 mode
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:00 +0000 (20:49 +0000)]
fix SVP64Asm Rc=1 assembly
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:47:48 +0000 (20:47 +0000)]
add black-box attribute to 4k SRAM cell
Cesar Strauss [Sat, 20 Feb 2021 18:39:41 +0000 (15:39 -0300)]
Fix more MSB0 issues in comments
Cesar Strauss [Sat, 20 Feb 2021 18:31:55 +0000 (15:31 -0300)]
Replace more hardcoded constants with symbolic field numbers
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 16:40:41 +0000 (16:40 +0000)]
increment CRs based on srcstep, see what happens
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:22:18 +0000 (15:22 +0000)]
add litex wishbone interconnect to 4x 4k SRAMs
also had to add one more of the massive DFF 512 byte SRAMs in order to cover
all the exception areas (0x900) without going into 4k SRAM area,
which litex demands to be on an aligned boundary
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:58:58 +0000 (14:58 +0000)]
add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer if enabled
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:39:14 +0000 (14:39 +0000)]
add option for QTY 4x 4k SRAM blocks (not added yet) to issuer_verilog
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:30:07 +0000 (14:30 +0000)]
add Wishbone-wrapped SPBlock_512W64B8W