Luke Kenneth Casson Leighton [Fri, 14 May 2021 12:04:17 +0000 (13:04 +0100)]
clear out request data on return to idle
Luke Kenneth Casson Leighton [Fri, 14 May 2021 11:09:55 +0000 (12:09 +0100)]
sort out LoadStore1 misalignment FSM, also required test function pi_ld
to be modified to understand exceptions. pi_st TODO
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:36:19 +0000 (11:36 +0100)]
remove minerva units previously missed in cleanout
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:30:53 +0000 (11:30 +0100)]
add misaligned load through MMU (which is incorrectly succeeding without error)
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:12:33 +0000 (22:12 +0100)]
minor rework of wb_get, make generic
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:02:32 +0000 (22:02 +0100)]
added STORE test in test_ldst_pi.py, and it worked straight off
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:01:54 +0000 (22:01 +0100)]
update comments in issuer.py regarding a 4th FSM
Luke Kenneth Casson Leighton [Thu, 13 May 2021 19:02:00 +0000 (20:02 +0100)]
yet more debug log stuff for DCache, this time on CacheRam, to discern
which SRAM the read/write request went to
Luke Kenneth Casson Leighton [Thu, 13 May 2021 19:01:20 +0000 (20:01 +0100)]
fix wb_get error where data was being corrupted
(not WB classic compliant)
Luke Kenneth Casson Leighton [Thu, 13 May 2021 17:05:01 +0000 (18:05 +0100)]
add read at different locations in test_ldst_pi.py
Luke Kenneth Casson Leighton [Thu, 13 May 2021 16:46:07 +0000 (17:46 +0100)]
add some data for MMU to actually look up
Luke Kenneth Casson Leighton [Thu, 13 May 2021 16:35:07 +0000 (17:35 +0100)]
ha, hilarious: swapped TLBUpdate output sizes db_out and pb_out.
Luke Kenneth Casson Leighton [Thu, 13 May 2021 15:39:33 +0000 (16:39 +0100)]
whoops TLBIE must *clear* the valid bit not set it. TLBUpdate
Luke Kenneth Casson Leighton [Thu, 13 May 2021 15:38:18 +0000 (16:38 +0100)]
more debug Display in dcache.py
Luke Kenneth Casson Leighton [Thu, 13 May 2021 13:14:43 +0000 (14:14 +0100)]
putting in a lot more debug print statements in DCache, investigation
Luke Kenneth Casson Leighton [Wed, 12 May 2021 19:15:35 +0000 (20:15 +0100)]
add dcache tlb / pte test
Luke Kenneth Casson Leighton [Wed, 12 May 2021 19:04:12 +0000 (20:04 +0100)]
set m_out.load from ldst_r(egister) in LoadStore1
Luke Kenneth Casson Leighton [Wed, 12 May 2021 18:48:23 +0000 (19:48 +0100)]
move dcache unit test to separate test_dcache.py
Luke Kenneth Casson Leighton [Wed, 12 May 2021 18:35:35 +0000 (19:35 +0100)]
experimentation with MMU-enabled LoadStore1 through PortInterface
added was a way to capture a snapshot of the incoming LD/ST request,
so that it can be re-presented after an MMU lookup.
Luke Kenneth Casson Leighton [Wed, 12 May 2021 14:33:04 +0000 (15:33 +0100)]
add debug info, update comments, disable dcache in test
all tracking down bugs in test_ldst_pi.py
Luke Kenneth Casson Leighton [Wed, 12 May 2021 14:07:09 +0000 (15:07 +0100)]
start doing virtual memory queries via PortInterface on LoadStore1
Luke Kenneth Casson Leighton [Wed, 12 May 2021 13:35:55 +0000 (14:35 +0100)]
whoops missing default zero (no idea how)
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:17:33 +0000 (13:17 +0100)]
addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:15:05 +0000 (13:15 +0100)]
bit of a hack to get test_mmu_dcache_pi.py operational.
if missing data from the mem dictionary in wb_get, return zero
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:04:51 +0000 (13:04 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:04:37 +0000 (13:04 +0100)]
no need for sel0
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:59:45 +0000 (11:59 +0100)]
pass through MSR.PR through PortInterface, into LoadStore1
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:52:53 +0000 (11:52 +0100)]
connect MSR.PR to PortInterface in LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:46:33 +0000 (11:46 +0100)]
add msr_pr bit in PortInterface
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:44:42 +0000 (11:44 +0100)]
add MSR to LD/ST Input Record
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:07:55 +0000 (11:07 +0100)]
comment tidyup
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:05:57 +0000 (11:05 +0100)]
must also pass through instruction fault exception in LoadStore1
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:04:25 +0000 (11:04 +0100)]
whoops names changed in MMU FSM
Luke Kenneth Casson Leighton [Tue, 11 May 2021 09:56:56 +0000 (10:56 +0100)]
tidyup comments and remove LoadStore COMPLETE state
Luke Kenneth Casson Leighton [Tue, 11 May 2021 09:53:34 +0000 (10:53 +0100)]
cleanup on exception setting
Luke Kenneth Casson Leighton [Tue, 11 May 2021 09:45:29 +0000 (10:45 +0100)]
rename LoadStore1 data structures back to microwatt names
Luke Kenneth Casson Leighton [Mon, 10 May 2021 23:43:17 +0000 (00:43 +0100)]
add block for MMU activation to LoadStore1
Luke Kenneth Casson Leighton [Mon, 10 May 2021 23:35:18 +0000 (00:35 +0100)]
move LoadStore1 d_validblip setting, and get MMU_LOOKUP to re-run
the dcache request after the MMU_LOOKUP succeeds
Luke Kenneth Casson Leighton [Mon, 10 May 2021 23:25:53 +0000 (00:25 +0100)]
whoops, indentation issue on m.If/m.Else in dcache.py
Tobias Platen [Mon, 10 May 2021 17:41:58 +0000 (19:41 +0200)]
style-wise: use ~self.instr_fault not self.instr_fault==0
Tobias Platen [Mon, 10 May 2021 17:23:19 +0000 (19:23 +0200)]
LoadStore1: add rules for MMU_LOOKUP
Luke Kenneth Casson Leighton [Mon, 10 May 2021 13:15:49 +0000 (14:15 +0100)]
add links to set associative image, and bugreport
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:41:22 +0000 (20:41 +0100)]
add comments on translation of MMU_LOOKUP
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:34:39 +0000 (20:34 +0100)]
install MMU_LOOKUP vhdl to be translated to nmigen
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:32:45 +0000 (20:32 +0100)]
move (unused) ACK_WAIT code into FSM
remove another (unneeded) state, FINISH_LFS
sort-of got ACK_WAIT to flip over to IDLE but done has to be
asserted for longer than necessary. needs investigating
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:14:28 +0000 (20:14 +0100)]
add comments in LoadStore1
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:09:45 +0000 (20:09 +0100)]
remove invalid setting of d_in.valid from self.mmureq
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:05:42 +0000 (20:05 +0100)]
no SECOND_REQ
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:04:35 +0000 (20:04 +0100)]
remove SECOND_REQ
Tobias Platen [Sun, 9 May 2021 18:57:31 +0000 (20:57 +0200)]
src/soc/fu/ldst/loadstore.py drive output d_in.valid
Tobias Platen [Sun, 9 May 2021 17:00:50 +0000 (19:00 +0200)]
move skeleton to elaborate
Tobias Platen [Sun, 9 May 2021 16:57:55 +0000 (18:57 +0200)]
src/soc/fu/ldst/loadstore.py: add skeleton for fsm
Luke Kenneth Casson Leighton [Sun, 9 May 2021 15:48:29 +0000 (16:48 +0100)]
add comment about LD/ST exception needs copying into PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 9 May 2021 15:47:34 +0000 (16:47 +0100)]
run LD/ST Exception test case for MMU
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:45:17 +0000 (15:45 +0100)]
add MMU bugtracker link
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:42:09 +0000 (15:42 +0100)]
git submodule update
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:34:55 +0000 (15:34 +0100)]
update code-comments
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:30:25 +0000 (15:30 +0100)]
add in alignment exception capture/reporting in LoadStore1
Luke Kenneth Casson Leighton [Sun, 9 May 2021 12:30:49 +0000 (13:30 +0100)]
preference is to create a temp variable for comb and sync and use that
Luke Kenneth Casson Leighton [Sun, 9 May 2021 12:29:19 +0000 (13:29 +0100)]
add misalign flag to PortInterfaceBase
allows first exception to be generated
Luke Kenneth Casson Leighton [Sat, 8 May 2021 19:17:19 +0000 (20:17 +0100)]
LoadStore1 tidyup
Luke Kenneth Casson Leighton [Sat, 8 May 2021 19:15:34 +0000 (20:15 +0100)]
transferring more over to LoadStore FSM
Luke Kenneth Casson Leighton [Sat, 8 May 2021 19:08:02 +0000 (20:08 +0100)]
start putting state info into LoadStore1, slowly putting loadstore1.vhdl
FSM into LoadStore1
Luke Kenneth Casson Leighton [Sat, 8 May 2021 19:00:10 +0000 (20:00 +0100)]
add LoadStore State enum
Luke Kenneth Casson Leighton [Sat, 8 May 2021 00:43:43 +0000 (01:43 +0100)]
add bugreport link to mmu
Tobias Platen [Fri, 7 May 2021 18:39:37 +0000 (20:39 +0200)]
fix 'sync' referenced before assignment in src/soc/fu/mmu/fsm.py
Luke Kenneth Casson Leighton [Fri, 7 May 2021 17:53:29 +0000 (18:53 +0100)]
start setting DSISR bits but commented out
Luke Kenneth Casson Leighton [Fri, 7 May 2021 12:26:21 +0000 (13:26 +0100)]
update comments and docstrings
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:51:56 +0000 (12:51 +0100)]
whoops, import error
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:51:26 +0000 (12:51 +0100)]
move LoadStore1 class to soc.fu.ldst.loadstore
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:44:07 +0000 (12:44 +0100)]
whoops was still copying output over in CommonOutputStage
for SVP64 pred-zero-dest
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:40:41 +0000 (12:40 +0100)]
how we managed to get this far without noticing that test_runner.py is
not using "with self.subTest" is anyones guess
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:37:17 +0000 (12:37 +0100)]
move dsisr and dar into LoadStore1
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:19:26 +0000 (12:19 +0100)]
move zero-dest-pred in Common Output Stage to not copy target.
this then allows CR0 to set a "zero" bit
Luke Kenneth Casson Leighton [Fri, 7 May 2021 11:15:48 +0000 (12:15 +0100)]
whoops setup of core.sv_pred_sm/dm not indented and under "if svp64_en"
Luke Kenneth Casson Leighton [Thu, 6 May 2021 17:52:50 +0000 (18:52 +0100)]
whoops disabled tests agaaaaain
Luke Kenneth Casson Leighton [Thu, 6 May 2021 17:52:24 +0000 (18:52 +0100)]
pass relevant predicate mask bits through to Decoders (PowerDecoderSubset)
at the right time
Luke Kenneth Casson Leighton [Thu, 6 May 2021 17:45:43 +0000 (18:45 +0100)]
add in predicate mask bit detection when zeroing is enabled
Luke Kenneth Casson Leighton [Thu, 6 May 2021 17:06:47 +0000 (18:06 +0100)]
pass SVP64 ReMap field through to core and then on to FU decoders
Luke Kenneth Casson Leighton [Thu, 6 May 2021 12:40:28 +0000 (13:40 +0100)]
moved exts* SVP64 unit tests to a different location
Jonathan Neuschäfer [Mon, 3 May 2021 19:53:26 +0000 (21:53 +0200)]
.gitlab-ci.yml: Increase the build timeout
The job takes longer than an hour on gitlab.com, so let's set the
timeout to two hours, to be sure that there's enough time.
On other GitLab-CI runners, it will be faster, but it's good to be able
to run the tests on gitlab.com too.
Luke Kenneth Casson Leighton [Thu, 6 May 2021 04:02:31 +0000 (05:02 +0100)]
argh someobe falsely stated in the README that LibreSOC is an "open"
project.
Luke Kenneth Casson Leighton [Wed, 5 May 2021 15:33:48 +0000 (16:33 +0100)]
if zeroing is set, put zero into input or output as requested
Tobias Platen [Wed, 5 May 2021 17:56:53 +0000 (19:56 +0200)]
fix bug in mmu/fsm.py
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:36:07 +0000 (14:36 +0100)]
simplify README.md so that it gets submitted to pypi
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:19:23 +0000 (14:19 +0100)]
mark long description type as markdown
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:17:59 +0000 (14:17 +0100)]
update NEWS.txt
Luke Kenneth Casson Leighton [Wed, 5 May 2021 13:16:58 +0000 (14:16 +0100)]
add libresoc-openpower-isa to setup.py dependencies
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:38:39 +0000 (13:38 +0100)]
put sv_input_record_layout onto CompOpSubsetBase after all
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:38:11 +0000 (13:38 +0100)]
whoops wrong signal name, set exc_happened
Luke Kenneth Casson Leighton [Wed, 5 May 2021 11:51:26 +0000 (12:51 +0100)]
add SVP64 RM fields to ALU input record
Tobias Platen [Tue, 4 May 2021 19:25:22 +0000 (21:25 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 4 May 2021 19:23:32 +0000 (21:23 +0200)]
implement MFSPR the same way as fu/spr/main_stage.py
Luke Kenneth Casson Leighton [Tue, 4 May 2021 19:21:04 +0000 (20:21 +0100)]
remove minerva debug unit (not needed)
Jonathan Neuschäfer [Tue, 4 May 2021 11:09:49 +0000 (13:09 +0200)]
minerva tests: Don't import soc.minerva.csr
Fixes: 4af6717b ("remove unneeded minerva code")
Jonathan Neuschäfer [Tue, 4 May 2021 08:03:17 +0000 (10:03 +0200)]
.gitlab-ci.yml: Silence pywriter harder
"make -j$(nproc) pywriter" and "pywriter" fill the log with over 20000
lines like this:
> /builds/neuschaefer/soc/openpower-isa/src/openpower/decoder/power_decoder.py:420: UnusedElaboratable: <openpower.decoder.power_decoder.PowerDecoder object at 0x7f4bf8ae8e48> created but never used
> row_subset=self.row_subsetfn)
> UnusedElaboratable: Enable tracemalloc to get the object allocation traceback
Ideally, the relevant code should be fixed to avoid this warning, but for now,
I'm silencing it, so I can fit more relevant output into GitLab-CI's 4 MiB limit.
Jonathan Neuschäfer [Tue, 4 May 2021 06:19:29 +0000 (08:19 +0200)]
.gitlab-ci.yml: Trim log output
GitLab-CI limits log output to 4 MiB, which the build job currently
exceeds. Trim the output of some of the earlier steps, to make it
possible to figure out what went wrong in the later steps.
Jonathan Neuschäfer [Mon, 3 May 2021 21:14:35 +0000 (23:14 +0200)]
.gitlab-ci.yml: Fix invocation of pywriter
See
ffb6288f ("svanalysis and pywriter now command-line scripts").
Jonathan Neuschäfer [Tue, 4 May 2021 10:57:26 +0000 (12:57 +0200)]
.gitlab-ci.yml: Clone and build power-instruction-analyzer
Jonathan Neuschäfer [Tue, 4 May 2021 10:28:56 +0000 (12:28 +0200)]
.gitlab-ci.yml: Clone and build c4m-jtag