soclayout.git
3 years agosubmodule update
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 21:12:03 +0000 (21:12 +0000)]
submodule update

3 years agoadd spimaster to peripheral system, all names changed. wtf?? sigh
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 15:51:10 +0000 (15:51 +0000)]
add spimaster to peripheral system, all names changed. wtf?? sigh

3 years agoupdated non_generated pinmap json file
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 12:01:41 +0000 (12:01 +0000)]
updated non_generated pinmap json file

3 years agoupdated non_generated pinmap json file
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:55:00 +0000 (11:55 +0000)]
updated non_generated pinmap json file

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:54:14 +0000 (11:54 +0000)]
update submodule

3 years agoargh, nsxlib does not have analog. have to cheat
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:50:02 +0000 (11:50 +0000)]
argh, nsxlib does not have analog.  have to cheat

3 years agosubmodule update
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 11:13:54 +0000 (11:13 +0000)]
submodule update

3 years agoRebame root clock signal from "core.por_clk" into "core.pll_clk".
Jean-Paul Chaput [Thu, 10 Jun 2021 09:17:20 +0000 (11:17 +0200)]
Rebame root clock signal from "core.por_clk" into "core.pll_clk".

3 years agosys_clk renamed to sys_pllclk, iopads load from copy of auto-generated
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:29:25 +0000 (19:29 +0000)]
sys_clk renamed to sys_pllclk, iopads load from copy of auto-generated
pinouts in json format

3 years agoadd litex pinpads JSON file to nongenerated
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:10:35 +0000 (19:10 +0000)]
add litex pinpads JSON file to nongenerated

3 years agodoh, should have reduced NC by 16
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:09:20 +0000 (19:09 +0000)]
doh, should have reduced NC by 16

3 years agopll24_i renamed to clk_24_i
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:43:34 +0000 (15:43 +0000)]
pll24_i renamed to clk_24_i

3 years agopllclk_o is renamed to pllclk_clk
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:41:47 +0000 (15:41 +0000)]
pllclk_o is renamed to pllclk_clk

3 years agouse sys_pllclk_from_pad not sys_clk_from_pad
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:23:34 +0000 (15:23 +0000)]
use sys_pllclk_from_pad not sys_clk_from_pad
rename module ls180

3 years agosys_clk renamed to sys_pllclk
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:20:36 +0000 (15:20 +0000)]
sys_clk renamed to sys_pllclk

3 years agoreorg of PLL, routed out into peripheral interconnect
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:19:50 +0000 (15:19 +0000)]
reorg of PLL, routed out into peripheral interconnect
then manually connected up
needed a rename of sys_clk to sys_pllclk to not conflict

3 years agoI/O pads reorganisation, 32 per side (except for NORTH).
Jean-Paul Chaput [Wed, 9 Jun 2021 09:50:37 +0000 (11:50 +0200)]
I/O pads reorganisation, 32 per side (except for NORTH).

3 years agoP&R tweaks for routing convergence.
Jean-Paul Chaput [Wed, 9 Jun 2021 09:14:33 +0000 (11:14 +0200)]
P&R tweaks for routing convergence.

3 years agoAdd a case in the build script to fit my environment (jpc).
Jean-Paul Chaput [Wed, 9 Jun 2021 09:13:27 +0000 (11:13 +0200)]
Add a case in the build script to fit my environment (jpc).

3 years agoRemove files that are now copied from other locations.
Jean-Paul Chaput [Wed, 9 Jun 2021 09:02:51 +0000 (11:02 +0200)]
Remove files that are now copied from other locations.

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 8 Jun 2021 11:15:46 +0000 (13:15 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoAdpapt e9/TSMC doDesign to the new size of the SRAMs (jumpers).
Jean-Paul Chaput [Tue, 8 Jun 2021 11:14:32 +0000 (13:14 +0200)]
Adpapt e9/TSMC doDesign to the new size of the SRAMs (jumpers).

3 years agoargh, nsxlib cannot cope with 3 clocks!
Luke Kenneth Casson Leighton [Sun, 6 Jun 2021 14:01:16 +0000 (14:01 +0000)]
argh, nsxlib cannot cope with 3 clocks!

3 years agoadd vss/vdd as pins, gets the net into the VST
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:45:00 +0000 (17:45 +0000)]
add vss/vdd as pins, gets the net into the VST

3 years agoset power type in fake pll vdd/vss
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:38:04 +0000 (17:38 +0000)]
set power type in fake pll vdd/vss

3 years agowhoops, fake pll/mem need vss/vdd
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:34:32 +0000 (17:34 +0000)]
whoops, fake pll/mem need vss/vdd

3 years agowhoops naming pads different from nets is important
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:09:01 +0000 (17:09 +0000)]
whoops naming pads different from nets is important

3 years agosigh trying to find the right clock line
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 17:08:44 +0000 (17:08 +0000)]
sigh trying to find the right clock line

3 years agomore comments
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 12:53:26 +0000 (12:53 +0000)]
more comments

3 years agocomment about por_clk
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 12:20:00 +0000 (12:20 +0000)]
comment about por_clk

3 years agocorrect clock name for H-Tree in ls180
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 12:19:02 +0000 (12:19 +0000)]
correct clock name for H-Tree in ls180
use por_clk not core.por_clk
this is the output from the PLL

3 years agosort out clock names in experiments10_verilog
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 11:30:42 +0000 (11:30 +0000)]
sort out clock names in experiments10_verilog

3 years agoadd coresync_clk to list of HTree
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 11:09:54 +0000 (11:09 +0000)]
add coresync_clk to list of HTree

3 years agoadd dummy pll to experiments10_verilog
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 11:04:27 +0000 (11:04 +0000)]
add dummy pll to experiments10_verilog

3 years agoset various clocks to use H-Tree
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 10:23:39 +0000 (10:23 +0000)]
set various clocks to use H-Tree

3 years agoadd dummy (fake) PLL to experiments10_verilog for testing
Luke Kenneth Casson Leighton [Sat, 5 Jun 2021 10:15:23 +0000 (10:15 +0000)]
add dummy (fake) PLL to experiments10_verilog for testing

3 years agoUpdated experiments12 for the latest Coriolis.
Jean-Paul Chaput [Fri, 4 Jun 2021 19:12:29 +0000 (21:12 +0200)]
Updated experiments12 for the latest Coriolis.

* To serve as a test bench for the reamining diode insertion
  problems.

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Fri, 4 Jun 2021 16:15:38 +0000 (18:15 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoUpdated configuration suited for experiment9/tsmc_c018.
Jean-Paul Chaput [Fri, 4 Jun 2021 16:09:32 +0000 (18:09 +0200)]
Updated configuration suited for experiment9/tsmc_c018.

* Typo in coriolis2/settings.py (extra 'e' in blackboxNames parameter).
* Disable blackboxes generation in TSMC, they are directly supplied by
  the FlexLib DK.
* Strip the Makefile from unusable targets in real mode.
* Update doDesign.py for the latest Coriolis (H-Tree).

3 years agoadd 4ksram recon script in tsmc_c018 as well
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 22:29:03 +0000 (22:29 +0000)]
add 4ksram recon script in tsmc_c018 as well

3 years agoadd build_full_4ksram_recon.sh to copy over Staf re-connected PLL
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 21:56:54 +0000 (21:56 +0000)]
add build_full_4ksram_recon.sh to copy over Staf re-connected PLL

3 years agorename sys_clk to sys_clk_0 and rename ref_clk to sys_clk
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 21:52:45 +0000 (21:52 +0000)]
rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk
this restores ls180 module to minimise changes

3 years agoReroute clk so PLL output clock is used as sys_clk.
Staf Verhaegen [Thu, 3 Jun 2021 19:59:56 +0000 (21:59 +0200)]
Reroute clk so PLL output clock is used as sys_clk.

3 years agoDuplicate file before patching for clock rerouting.
Staf Verhaegen [Thu, 3 Jun 2021 19:55:55 +0000 (21:55 +0200)]
Duplicate file before patching for clock rerouting.

3 years agorename ref in fake-pll to ref_v
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:14:33 +0000 (15:14 +0000)]
rename ref in fake-pll to ref_v

3 years agoupdate libresoc.v to use sys_clk for main core
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:07:27 +0000 (15:07 +0000)]
update libresoc.v to use sys_clk for main core

3 years agochange ref to ref_v in PLL (keyword)
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:07:03 +0000 (15:07 +0000)]
change ref to ref_v in PLL (keyword)

3 years agoset other nets to input in fake 4k SRAM cell
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:59:36 +0000 (13:59 +0000)]
set other nets to input in fake 4k SRAM cell

3 years agoadd TODO into tsmc_c018 coriolis2 settings.py
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:53:17 +0000 (13:53 +0000)]
add TODO into tsmc_c018 coriolis2 settings.py

3 years agoupdate libresoc.v
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:52:56 +0000 (13:52 +0000)]
update libresoc.v

3 years agoset fake-mem LibreSOCMem output q as a Net Output
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:52:36 +0000 (13:52 +0000)]
set fake-mem LibreSOCMem output q as a Net Output

3 years agoset fake PLL Master Cell directions explicitly
Luke Kenneth Casson Leighton [Thu, 27 May 2021 13:50:12 +0000 (13:50 +0000)]
set fake PLL Master Cell directions explicitly

3 years agoclk_sel_i in TestIssuer was one bit not 2
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:13:00 +0000 (15:13 +0000)]
clk_sel_i in TestIssuer was one bit not 2

3 years agoremove sram4k wb err (unused anyway)
Luke Kenneth Casson Leighton [Wed, 26 May 2021 14:07:13 +0000 (14:07 +0000)]
remove sram4k wb err (unused anyway)

3 years agoappears to be missing libresoc from NETLISTS in Makefile
Luke Kenneth Casson Leighton [Wed, 26 May 2021 13:46:01 +0000 (13:46 +0000)]
appears to be missing libresoc from NETLISTS in Makefile

3 years agoattempt better grid alignment for fake cells
Luke Kenneth Casson Leighton [Tue, 25 May 2021 15:01:46 +0000 (15:01 +0000)]
attempt better grid alignment for fake cells

3 years agochange cell sizes to grid layout (?)
Luke Kenneth Casson Leighton [Tue, 25 May 2021 12:01:44 +0000 (12:01 +0000)]
change cell sizes to grid layout (?)

3 years agoincrease not-connected pads by one
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:45:59 +0000 (11:45 +0000)]
increase not-connected pads by one

3 years agoadd fake pll symlink
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:39:00 +0000 (11:39 +0000)]
add fake pll symlink

3 years agorename pll out signal to out_v in "fake" pll cell
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:37:47 +0000 (11:37 +0000)]
rename pll out signal to out_v in "fake" pll cell

3 years agorename PLL out to out_v in test_issuer
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:32:58 +0000 (11:32 +0000)]
rename PLL out to out_v in test_issuer

3 years agorename pll blackbox out to out_v
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:30:07 +0000 (11:30 +0000)]
rename pll blackbox out to out_v

3 years agodisappearing signal from pll, attempt to get it back
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:45:12 +0000 (17:45 +0000)]
disappearing signal from pll, attempt to get it back

3 years agoremove "*" net from fake-pll cell, it ends up in the vst file
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:35:37 +0000 (17:35 +0000)]
remove "*" net from fake-pll cell, it ends up in the vst file

3 years agoround to 0.135 cell grid?
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:27:40 +0000 (17:27 +0000)]
round to 0.135 cell grid?

3 years agorename cell to "real_pll" to avoid conflict with cell also named "pll"
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:25:35 +0000 (17:25 +0000)]
rename cell to "real_pll" to avoid conflict with cell also named "pll"

3 years agoadd dummy/fake/ghost PLL blackbox cell
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:00:20 +0000 (17:00 +0000)]
add dummy/fake/ghost PLL blackbox cell
to nsxlib experiments9.  based on the dummy/fake/ghost/symbolic
LibreSOCMem previously created
the cell is completely empty, the only important thing is the *existence*
of the cell and its I/O connections

3 years agorename PLL pad names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 12:06:24 +0000 (12:06 +0000)]
rename PLL pad names

3 years agocorrect PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:59:32 +0000 (11:59 +0000)]
correct PLL names

3 years agore-add 4k sram
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:44:49 +0000 (11:44 +0000)]
re-add 4k sram

3 years agoannoying rename of pll analog pin
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:36:16 +0000 (11:36 +0000)]
annoying rename of pll analog pin

3 years agomanually rename ls180sram4k module to ls180
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:15:36 +0000 (11:15 +0000)]
manually rename ls180sram4k module to ls180

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:03:08 +0000 (11:03 +0000)]
submodule update

3 years agoupdate PLL to use submodule Instance
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:02:59 +0000 (11:02 +0000)]
update PLL to use submodule Instance

3 years agodo an SRAM search by looking for matching along the path
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 17:47:47 +0000 (17:47 +0000)]
do an SRAM search by looking for matching along the path
goodbye explicit yosys ids!

3 years ago4k sram build
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 17:17:54 +0000 (17:17 +0000)]
4k sram build

3 years agouse "make view" not "make vst"
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 17:05:18 +0000 (17:05 +0000)]
use "make view" not "make vst"

3 years agoadd fake LibreSOCMem library to freepdk_c4m45
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 12:40:09 +0000 (12:40 +0000)]
add fake LibreSOCMem library to freepdk_c4m45

3 years agoadd symlink to "fake" LibreSOCMem
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 12:35:56 +0000 (12:35 +0000)]
add symlink to "fake" LibreSOCMem

3 years agoenabling experiments9 new LibreSOCMem fake blackbox SRAM
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 11:42:30 +0000 (11:42 +0000)]
enabling experiments9 new LibreSOCMem fake blackbox SRAM

3 years agousing renamed (single) spblock_512w64b8w
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 10:55:24 +0000 (10:55 +0000)]
using renamed (single) spblock_512w64b8w

3 years agousing new single spblock_512xxx in experiments9
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 10:54:34 +0000 (10:54 +0000)]
using new single spblock_512xxx in experiments9

3 years agoadd complete series of pins onto fake SRAM
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 10:51:11 +0000 (10:51 +0000)]
add complete series of pins onto fake SRAM

3 years agofirst experiment creating a LibreSOCMem library with a cell real_mem
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 18:40:50 +0000 (18:40 +0000)]
first experiment creating a LibreSOCMem library with a cell real_mem
based on FlexLib

3 years agocreate function which pre-creates the blackbox cells
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 17:29:01 +0000 (17:29 +0000)]
create function which pre-creates the blackbox cells
use it to create createPLLBlackbox, not called yet

3 years agoname everything back to spblock_512w64b8w now that missing blackbox
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 17:22:57 +0000 (17:22 +0000)]
name everything back to spblock_512w64b8w now that missing blackbox
cell issue has been found

3 years agorename spblock modules to just straight spblock_512w64b8w after
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 17:01:18 +0000 (17:01 +0000)]
rename spblock modules to just straight spblock_512w64b8w after
JP sorted blackbox module loading

3 years agoalso add createSRAMblocks to freepdk_c4m45
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 16:57:33 +0000 (16:57 +0000)]
also add createSRAMblocks to freepdk_c4m45

3 years agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Wed, 28 Apr 2021 14:07:47 +0000 (16:07 +0200)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 years agoManagement of SRAMs block at Coriolis devel.
Jean-Paul Chaput [Wed, 28 Apr 2021 14:02:13 +0000 (16:02 +0200)]
Management of SRAMs block at Coriolis devel.

Sub block instanciating the real SRAM are added on the fly to the
Yosys blackboxes spblock512w64b8w_X. Must be done *before* ls180
loading.

3 years agoadd vbe spblock models to non_generated and build scripts
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 10:15:41 +0000 (10:15 +0000)]
add vbe spblock models to non_generated and build scripts

3 years agoshrinking regfile sizes some more
Luke Kenneth Casson Leighton [Wed, 28 Apr 2021 10:15:13 +0000 (10:15 +0000)]
shrinking regfile sizes some more

3 years agoadd blackbox attribute to spblock512*.v
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 16:21:49 +0000 (16:21 +0000)]
add blackbox attribute to spblock512*.v

3 years agoalso add blackboxes spblock512* etc.
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 11:56:31 +0000 (11:56 +0000)]
also add blackboxes spblock512* etc.

3 years agoadd copying over of spblock*.v and pll.v to build scripts
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 10:54:49 +0000 (10:54 +0000)]
add copying over of spblock*.v and pll.v to build scripts

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 16:30:50 +0000 (16:30 +0000)]
submodule update

3 years agoCorrect setup for experiment9/freepdk_c4m45, restrict to 6 metals.
Jean-Paul Chaput [Sun, 25 Apr 2021 11:16:57 +0000 (13:16 +0200)]
Correct setup for experiment9/freepdk_c4m45, restrict to 6 metals.

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:47:15 +0000 (20:47 +0000)]
update submodule

3 years agocleanup mksyms.sh to include FreePDK_C4M45
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 13:55:14 +0000 (13:55 +0000)]
cleanup mksyms.sh to include FreePDK_C4M45

3 years agoadd export of PDKMASTER_TOP to experiments9/freepdk_c4m45
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 13:53:09 +0000 (13:53 +0000)]
add export of PDKMASTER_TOP to experiments9/freepdk_c4m45