soc.git
3 years agodcache: add debug output
Tobias Platen [Sun, 20 Jun 2021 17:31:34 +0000 (19:31 +0200)]
dcache: add debug output

3 years agoupdate test_ldst_pi.py
Tobias Platen [Sun, 20 Jun 2021 16:00:22 +0000 (18:00 +0200)]
update test_ldst_pi.py

3 years agouncomment test_dcache_random
Tobias Platen [Fri, 18 Jun 2021 18:09:54 +0000 (20:09 +0200)]
uncomment test_dcache_random

3 years agosrc/soc/fu/ldst/loadstore.py: keep data for the whole cycle
Tobias Platen [Fri, 18 Jun 2021 17:40:05 +0000 (19:40 +0200)]
src/soc/fu/ldst/loadstore.py: keep data for the whole cycle

3 years agoupdate testcase for ldst
Tobias Platen [Mon, 14 Jun 2021 18:02:49 +0000 (20:02 +0200)]
update testcase for ldst

3 years agowhoops Popcount datalen too big (wasted bits). reduce
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 19:10:16 +0000 (20:10 +0100)]
whoops Popcount datalen too big (wasted bits). reduce

3 years agogit submodule update
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:51:14 +0000 (16:51 +0100)]
git submodule update

3 years agodisconnect pll clock, connected in peripheral interconnect
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:08:25 +0000 (16:08 +0100)]
disconnect pll clock, connected in peripheral interconnect

3 years agoadd in/out of ref_clk and pllclk_clk when PLL enabled
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:32:26 +0000 (14:32 +0100)]
add in/out of ref_clk and pllclk_clk when PLL enabled

3 years agoStart a new self-contained test suite for LDSTCompUnit
Cesar Strauss [Sun, 6 Jun 2021 22:00:46 +0000 (19:00 -0300)]
Start a new self-contained test suite for LDSTCompUnit

The idea is to use parallel processes, like on the new ALU CompUnit tests.
In this case, it will include PortInterface emulation as well.
The current goal is to ensure that exception support is properly
implemented.

3 years agocomment out domains that have already been created
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 15:36:40 +0000 (16:36 +0100)]
comment out domains that have already been created

3 years agono, do not assign clock to clock!
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:48:14 +0000 (15:48 +0100)]
no, do not assign clock to clock!

3 years agorename ref to ref_v in PLL due to ref being a verilog keyword
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:42:32 +0000 (15:42 +0100)]
rename ref to ref_v in PLL due to ref being a verilog keyword

3 years agosort out PLL domains but bypass PLL due to lack of time
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:41:33 +0000 (15:41 +0100)]
sort out PLL domains but bypass PLL due to lack of time

3 years agouse DomainRenamer on all sub-components of TestIssuer
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 12:48:32 +0000 (13:48 +0100)]
use DomainRenamer on all sub-components of TestIssuer
except for JTAG and DMI

3 years agomake core_rst a member of TestIssuerInternal
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 12:02:59 +0000 (13:02 +0100)]
make core_rst a member of TestIssuerInternal

3 years agotest_ldst_pi.py: add new test case
Tobias Platen [Tue, 1 Jun 2021 18:23:37 +0000 (20:23 +0200)]
test_ldst_pi.py: add new test case

3 years agotest_ldst_pi.py: first version of test_dcache_random()
Tobias Platen [Sat, 29 May 2021 18:46:18 +0000 (20:46 +0200)]
test_ldst_pi.py: first version of test_dcache_random()

3 years agotest_ldst_pi.py: more test_dcache_regression()
Tobias Platen [Sat, 29 May 2021 18:10:15 +0000 (20:10 +0200)]
test_ldst_pi.py: more test_dcache_regression()

3 years agoadjust PLL connections looking for coriolis2 issue
Luke Kenneth Casson Leighton [Thu, 27 May 2021 17:21:16 +0000 (18:21 +0100)]
adjust PLL connections looking for coriolis2 issue

3 years agocorrections on spblock ack
Luke Kenneth Casson Leighton [Thu, 27 May 2021 12:04:10 +0000 (13:04 +0100)]
corrections on spblock ack

3 years agoclassic wishbone mode: must not do ack if already acked
Luke Kenneth Casson Leighton [Thu, 27 May 2021 12:01:42 +0000 (13:01 +0100)]
classic wishbone mode: must not do ack if already acked

3 years agoarse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:10:30 +0000 (16:10 +0100)]
arse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2

3 years agoremove err feature from sram4k wb
Luke Kenneth Casson Leighton [Wed, 26 May 2021 15:09:58 +0000 (16:09 +0100)]
remove err feature from sram4k wb

3 years agoadd ldst PortInterface misalign unit test (underway)
Luke Kenneth Casson Leighton [Wed, 26 May 2021 13:22:45 +0000 (14:22 +0100)]
add ldst PortInterface misalign unit test (underway)

3 years agorename PLL signals
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:31:31 +0000 (12:31 +0100)]
rename PLL signals

3 years agotest_ldst_pi.py: fix race condition causing early stop
Tobias Platen [Tue, 25 May 2021 19:00:41 +0000 (21:00 +0200)]
test_ldst_pi.py: fix race condition causing early stop

3 years agowait_ldok: add debug output count
Tobias Platen [Tue, 25 May 2021 17:22:46 +0000 (19:22 +0200)]
wait_ldok: add debug output count

3 years agowhoops sort out name of SPBlock RAM
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:21:00 +0000 (18:21 +0100)]
whoops sort out name of SPBlock RAM

3 years agochange name of submodule to real_pll
Luke Kenneth Casson Leighton [Mon, 24 May 2021 17:05:10 +0000 (18:05 +0100)]
change name of submodule to real_pll

3 years agomatch up PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:55:09 +0000 (12:55 +0100)]
match up PLL names

3 years agoRemove redundant build step
Cesar Strauss [Sat, 22 May 2021 21:12:48 +0000 (18:12 -0300)]
Remove redundant build step

The pywriter script has already ran, as part of the openpower-isa install.

3 years agoInclude missing step in automated build
Cesar Strauss [Sat, 22 May 2021 21:10:02 +0000 (18:10 -0300)]
Include missing step in automated build

The newly added pyfnwriter script needs to run just before pywriter.

3 years agoMove the reset code outside of the sub-test
Cesar Strauss [Sat, 22 May 2021 20:31:00 +0000 (17:31 -0300)]
Move the reset code outside of the sub-test

Even if a sub-test fails, the core still needs to be reset.
This code does not check any assertions, so it's safe to move it outside.

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:50:32 +0000 (11:50 +0100)]
update submodule

3 years agoupdate PLL to use Instance
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:50:25 +0000 (11:50 +0100)]
update PLL to use Instance

3 years agotest_ldst_pi.py: add dcache regression and random test from test_dcache.py
Tobias Platen [Sat, 15 May 2021 17:10:33 +0000 (19:10 +0200)]
test_ldst_pi.py: add dcache regression and random test from test_dcache.py

3 years agoadd radix MMU "miss" test
Luke Kenneth Casson Leighton [Fri, 14 May 2021 19:47:38 +0000 (20:47 +0100)]
add radix MMU "miss" test

3 years agoclear out request data on return to idle
Luke Kenneth Casson Leighton [Fri, 14 May 2021 12:04:17 +0000 (13:04 +0100)]
clear out request data on return to idle

3 years agosort out LoadStore1 misalignment FSM, also required test function pi_ld
Luke Kenneth Casson Leighton [Fri, 14 May 2021 11:09:55 +0000 (12:09 +0100)]
sort out LoadStore1 misalignment FSM, also required test function pi_ld
to be modified to understand exceptions.  pi_st TODO

3 years agoremove minerva units previously missed in cleanout
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:36:19 +0000 (11:36 +0100)]
remove minerva units previously missed in cleanout

3 years agoadd misaligned load through MMU (which is incorrectly succeeding without error)
Luke Kenneth Casson Leighton [Fri, 14 May 2021 10:30:53 +0000 (11:30 +0100)]
add misaligned load through MMU (which is incorrectly succeeding without error)

3 years agominor rework of wb_get, make generic
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:12:33 +0000 (22:12 +0100)]
minor rework of wb_get, make generic

3 years agoadded STORE test in test_ldst_pi.py, and it worked straight off
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:02:32 +0000 (22:02 +0100)]
added STORE test in test_ldst_pi.py, and it worked straight off

3 years agoupdate comments in issuer.py regarding a 4th FSM
Luke Kenneth Casson Leighton [Thu, 13 May 2021 21:01:54 +0000 (22:01 +0100)]
update comments in issuer.py regarding a 4th FSM

3 years agoyet more debug log stuff for DCache, this time on CacheRam, to discern
Luke Kenneth Casson Leighton [Thu, 13 May 2021 19:02:00 +0000 (20:02 +0100)]
yet more debug log stuff for DCache, this time on CacheRam, to discern
which SRAM the read/write request went to

3 years agofix wb_get error where data was being corrupted
Luke Kenneth Casson Leighton [Thu, 13 May 2021 19:01:20 +0000 (20:01 +0100)]
fix wb_get error where data was being corrupted
(not WB classic compliant)

3 years agoadd read at different locations in test_ldst_pi.py
Luke Kenneth Casson Leighton [Thu, 13 May 2021 17:05:01 +0000 (18:05 +0100)]
add read at different locations in test_ldst_pi.py

3 years agoadd some data for MMU to actually look up
Luke Kenneth Casson Leighton [Thu, 13 May 2021 16:46:07 +0000 (17:46 +0100)]
add some data for MMU to actually look up

3 years agoha, hilarious: swapped TLBUpdate output sizes db_out and pb_out.
Luke Kenneth Casson Leighton [Thu, 13 May 2021 16:35:07 +0000 (17:35 +0100)]
ha, hilarious: swapped TLBUpdate output sizes db_out and pb_out.

3 years agowhoops TLBIE must *clear* the valid bit not set it. TLBUpdate
Luke Kenneth Casson Leighton [Thu, 13 May 2021 15:39:33 +0000 (16:39 +0100)]
whoops TLBIE must *clear* the valid bit not set it.  TLBUpdate

3 years agomore debug Display in dcache.py
Luke Kenneth Casson Leighton [Thu, 13 May 2021 15:38:18 +0000 (16:38 +0100)]
more debug Display in dcache.py

3 years agoputting in a lot more debug print statements in DCache, investigation
Luke Kenneth Casson Leighton [Thu, 13 May 2021 13:14:43 +0000 (14:14 +0100)]
putting in a lot more debug print statements in DCache, investigation

3 years agoadd dcache tlb / pte test
Luke Kenneth Casson Leighton [Wed, 12 May 2021 19:15:35 +0000 (20:15 +0100)]
add dcache tlb / pte test

3 years agoset m_out.load from ldst_r(egister) in LoadStore1
Luke Kenneth Casson Leighton [Wed, 12 May 2021 19:04:12 +0000 (20:04 +0100)]
set m_out.load from ldst_r(egister) in LoadStore1

3 years agomove dcache unit test to separate test_dcache.py
Luke Kenneth Casson Leighton [Wed, 12 May 2021 18:48:23 +0000 (19:48 +0100)]
move dcache unit test to separate test_dcache.py

3 years agoexperimentation with MMU-enabled LoadStore1 through PortInterface
Luke Kenneth Casson Leighton [Wed, 12 May 2021 18:35:35 +0000 (19:35 +0100)]
experimentation with MMU-enabled LoadStore1 through PortInterface
added was a way to capture a snapshot of the incoming LD/ST request,
so that it can be re-presented after an MMU lookup.

3 years agoadd debug info, update comments, disable dcache in test
Luke Kenneth Casson Leighton [Wed, 12 May 2021 14:33:04 +0000 (15:33 +0100)]
add debug info, update comments, disable dcache in test
all tracking down bugs in test_ldst_pi.py

3 years agostart doing virtual memory queries via PortInterface on LoadStore1
Luke Kenneth Casson Leighton [Wed, 12 May 2021 14:07:09 +0000 (15:07 +0100)]
start doing virtual memory queries via PortInterface on LoadStore1

3 years agowhoops missing default zero (no idea how)
Luke Kenneth Casson Leighton [Wed, 12 May 2021 13:35:55 +0000 (14:35 +0100)]
whoops missing default zero (no idea how)

3 years agoaddcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:17:33 +0000 (13:17 +0100)]
addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)

3 years agobit of a hack to get test_mmu_dcache_pi.py operational.
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:15:05 +0000 (13:15 +0100)]
bit of a hack to get test_mmu_dcache_pi.py operational.
if missing data from the mem dictionary in wb_get, return zero

3 years agowhitespace
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:04:51 +0000 (13:04 +0100)]
whitespace

3 years agono need for sel0
Luke Kenneth Casson Leighton [Wed, 12 May 2021 12:04:37 +0000 (13:04 +0100)]
no need for sel0

3 years agopass through MSR.PR through PortInterface, into LoadStore1
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:59:45 +0000 (11:59 +0100)]
pass through MSR.PR through PortInterface, into LoadStore1

3 years agoconnect MSR.PR to PortInterface in LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:52:53 +0000 (11:52 +0100)]
connect MSR.PR to PortInterface in LDSTCompUnit

3 years agoadd msr_pr bit in PortInterface
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:46:33 +0000 (11:46 +0100)]
add msr_pr bit in PortInterface

3 years agoadd MSR to LD/ST Input Record
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:44:42 +0000 (11:44 +0100)]
add MSR to LD/ST Input Record

3 years agocomment tidyup
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:07:55 +0000 (11:07 +0100)]
comment tidyup

3 years agomust also pass through instruction fault exception in LoadStore1
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:05:57 +0000 (11:05 +0100)]
must also pass through instruction fault exception in LoadStore1

3 years agowhoops names changed in MMU FSM
Luke Kenneth Casson Leighton [Tue, 11 May 2021 10:04:25 +0000 (11:04 +0100)]
whoops names changed in MMU FSM

3 years agotidyup comments and remove LoadStore COMPLETE state
Luke Kenneth Casson Leighton [Tue, 11 May 2021 09:56:56 +0000 (10:56 +0100)]
tidyup comments and remove LoadStore COMPLETE state

3 years agocleanup on exception setting
Luke Kenneth Casson Leighton [Tue, 11 May 2021 09:53:34 +0000 (10:53 +0100)]
cleanup on exception setting

3 years agorename LoadStore1 data structures back to microwatt names
Luke Kenneth Casson Leighton [Tue, 11 May 2021 09:45:29 +0000 (10:45 +0100)]
rename LoadStore1 data structures back to microwatt names

3 years agoadd block for MMU activation to LoadStore1
Luke Kenneth Casson Leighton [Mon, 10 May 2021 23:43:17 +0000 (00:43 +0100)]
add block for MMU activation to LoadStore1

3 years agomove LoadStore1 d_validblip setting, and get MMU_LOOKUP to re-run
Luke Kenneth Casson Leighton [Mon, 10 May 2021 23:35:18 +0000 (00:35 +0100)]
move LoadStore1 d_validblip setting, and get MMU_LOOKUP to re-run
the dcache request after the MMU_LOOKUP succeeds

3 years agowhoops, indentation issue on m.If/m.Else in dcache.py
Luke Kenneth Casson Leighton [Mon, 10 May 2021 23:25:53 +0000 (00:25 +0100)]
whoops, indentation issue on m.If/m.Else in dcache.py

3 years agostyle-wise: use ~self.instr_fault not self.instr_fault==0
Tobias Platen [Mon, 10 May 2021 17:41:58 +0000 (19:41 +0200)]
style-wise: use ~self.instr_fault not self.instr_fault==0

3 years agoLoadStore1: add rules for MMU_LOOKUP
Tobias Platen [Mon, 10 May 2021 17:23:19 +0000 (19:23 +0200)]
LoadStore1: add rules for MMU_LOOKUP

3 years agoadd links to set associative image, and bugreport
Luke Kenneth Casson Leighton [Mon, 10 May 2021 13:15:49 +0000 (14:15 +0100)]
add links to set associative image, and bugreport

3 years agoadd comments on translation of MMU_LOOKUP
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:41:22 +0000 (20:41 +0100)]
add comments on translation of MMU_LOOKUP

3 years agoinstall MMU_LOOKUP vhdl to be translated to nmigen
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:34:39 +0000 (20:34 +0100)]
install MMU_LOOKUP vhdl to be translated to nmigen

3 years agomove (unused) ACK_WAIT code into FSM
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:32:45 +0000 (20:32 +0100)]
move (unused) ACK_WAIT code into FSM
remove another (unneeded) state, FINISH_LFS
sort-of got ACK_WAIT to flip over to IDLE but done has to be
asserted for longer than necessary. needs investigating

3 years agoadd comments in LoadStore1
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:14:28 +0000 (20:14 +0100)]
add comments in LoadStore1

3 years agoremove invalid setting of d_in.valid from self.mmureq
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:09:45 +0000 (20:09 +0100)]
remove invalid setting of d_in.valid from self.mmureq

3 years agono SECOND_REQ
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:05:42 +0000 (20:05 +0100)]
no SECOND_REQ

3 years agoremove SECOND_REQ
Luke Kenneth Casson Leighton [Sun, 9 May 2021 19:04:35 +0000 (20:04 +0100)]
remove SECOND_REQ

3 years agosrc/soc/fu/ldst/loadstore.py drive output d_in.valid
Tobias Platen [Sun, 9 May 2021 18:57:31 +0000 (20:57 +0200)]
src/soc/fu/ldst/loadstore.py drive output d_in.valid

3 years agomove skeleton to elaborate
Tobias Platen [Sun, 9 May 2021 17:00:50 +0000 (19:00 +0200)]
move skeleton to elaborate

3 years agosrc/soc/fu/ldst/loadstore.py: add skeleton for fsm
Tobias Platen [Sun, 9 May 2021 16:57:55 +0000 (18:57 +0200)]
src/soc/fu/ldst/loadstore.py: add skeleton for fsm

3 years agoadd comment about LD/ST exception needs copying into PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 9 May 2021 15:48:29 +0000 (16:48 +0100)]
add comment about LD/ST exception needs copying into PowerDecoder2

3 years agorun LD/ST Exception test case for MMU
Luke Kenneth Casson Leighton [Sun, 9 May 2021 15:47:34 +0000 (16:47 +0100)]
run LD/ST Exception test case for MMU

3 years agoadd MMU bugtracker link
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:45:17 +0000 (15:45 +0100)]
add MMU bugtracker link

3 years agogit submodule update
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:42:09 +0000 (15:42 +0100)]
git submodule update

3 years agoupdate code-comments
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:34:55 +0000 (15:34 +0100)]
update code-comments

3 years agoadd in alignment exception capture/reporting in LoadStore1
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:30:25 +0000 (15:30 +0100)]
add in alignment exception capture/reporting in LoadStore1

3 years agopreference is to create a temp variable for comb and sync and use that
Luke Kenneth Casson Leighton [Sun, 9 May 2021 12:30:49 +0000 (13:30 +0100)]
preference is to create a temp variable for comb and sync and use that

3 years agoadd misalign flag to PortInterfaceBase
Luke Kenneth Casson Leighton [Sun, 9 May 2021 12:29:19 +0000 (13:29 +0100)]
add misalign flag to PortInterfaceBase
allows first exception to be generated

3 years agoLoadStore1 tidyup
Luke Kenneth Casson Leighton [Sat, 8 May 2021 19:17:19 +0000 (20:17 +0100)]
LoadStore1 tidyup

3 years agotransferring more over to LoadStore FSM
Luke Kenneth Casson Leighton [Sat, 8 May 2021 19:15:34 +0000 (20:15 +0100)]
transferring more over to LoadStore FSM