soc.git
4 years agoFix missing 'comb +='
colepoirier [Sun, 7 Jun 2020 00:30:46 +0000 (17:30 -0700)]
Fix missing 'comb +='

4 years agoadd python3 env-var if not set in Makefile
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 23:04:30 +0000 (00:04 +0100)]
add python3 env-var if not set in Makefile

4 years agoexperimenting with setting up and testing memory
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 19:36:07 +0000 (20:36 +0100)]
experimenting with setting up and testing memory

4 years agoexpand regwid to 64 in l0_cache test
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:59:30 +0000 (19:59 +0100)]
expand regwid to 64 in l0_cache test

4 years agowork out how to initialise memory directly
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:46:41 +0000 (19:46 +0100)]
work out how to initialise memory directly

4 years agoinitialise L0 Memory from simulator memory
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:34:16 +0000 (19:34 +0100)]
initialise L0 Memory from simulator memory

4 years agowait a little for wr.rel to activate if wrmask is active
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 18:11:54 +0000 (19:11 +0100)]
wait a little for wr.rel to activate if wrmask is active

4 years agomissing test.mem arg for ISA in test_core
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:31:02 +0000 (18:31 +0100)]
missing test.mem arg for ISA in test_core

4 years agoallow Mem initialisation in ISACaller
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:28:36 +0000 (18:28 +0100)]
allow Mem initialisation in ISACaller

4 years agoshift-mask in Simulator Mem class not quite right
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:28:00 +0000 (18:28 +0100)]
shift-mask in Simulator Mem class not quite right

4 years agowrite-mask made from LD and Update mode (for data_o and addr_o output)
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 17:09:17 +0000 (18:09 +0100)]
write-mask made from LD and Update mode (for data_o and addr_o output)

4 years agoallow Mem in Simulator to be initialised
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 16:13:50 +0000 (17:13 +0100)]
allow Mem in Simulator to be initialised

4 years agouse name of unit to write simulator/vcd file
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 15:36:58 +0000 (16:36 +0100)]
use name of unit to write simulator/vcd file

4 years agoLDSTCompUnit test data structures linked up, starting debugging
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 15:33:53 +0000 (16:33 +0100)]
LDSTCompUnit test data structures linked up, starting debugging

4 years agoallow CompLDSTOpSubset to be passed through to LDSTCompUnit
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:45:14 +0000 (15:45 +0100)]
allow CompLDSTOpSubset to be passed through to LDSTCompUnit

4 years agoset up LDSTCompUnit using regspec
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:19:19 +0000 (15:19 +0100)]
set up LDSTCompUnit using regspec

4 years agoadd extra bugreport link
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:07:39 +0000 (15:07 +0100)]
add extra bugreport link

4 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:05:42 +0000 (15:05 +0100)]
whitespace

4 years agowhitespace indentation
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 14:04:11 +0000 (15:04 +0100)]
whitespace indentation

4 years agoadd special-case LDSTFunctionUnit
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 12:40:28 +0000 (13:40 +0100)]
add special-case LDSTFunctionUnit

4 years agowhoops dest%d_o not dest%d_i
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 12:40:11 +0000 (13:40 +0100)]
whoops dest%d_o not dest%d_i

4 years agoadd beginnings of LDST compunit test
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 12:28:02 +0000 (13:28 +0100)]
add beginnings of LDST compunit test

4 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 05:02:26 +0000 (06:02 +0100)]
whitespace

4 years agowhitespace / code-munge
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 05:00:38 +0000 (06:00 +0100)]
whitespace / code-munge

4 years agocomments / whitespace
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 04:56:15 +0000 (05:56 +0100)]
comments / whitespace

4 years agoupdate stage docstring
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 04:52:17 +0000 (05:52 +0100)]
update stage docstring

4 years agocode-munge
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 04:49:20 +0000 (05:49 +0100)]
code-munge

4 years agoremove unneeded imports
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 04:43:06 +0000 (05:43 +0100)]
remove unneeded imports

4 years agonoticed the regular pattern in all pipe_data.py (regspecs).
Luke Kenneth Casson Leighton [Sat, 6 Jun 2020 04:38:09 +0000 (05:38 +0100)]
noticed the regular pattern in all pipe_data.py (regspecs).
removed manual Input/Output Data, use regspecs to create it, in IntegerData

4 years agocomment out CR assertion for now
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 19:43:38 +0000 (20:43 +0100)]
comment out CR assertion for now

4 years agoAdded skeleton fu/trap/test/test_pipe_caller using
colepoirier [Fri, 5 Jun 2020 20:07:27 +0000 (13:07 -0700)]
Added skeleton fu/trap/test/test_pipe_caller using
fu/cr/test/test_pipe_caller as template

4 years agoAdd trap_input_data.py for fu/trap, cookie-cut from
colepoirier [Fri, 5 Jun 2020 19:55:33 +0000 (12:55 -0700)]
Add trap_input_data.py for fu/trap, cookie-cut from
fu/cr/cr_input_record with all 'CR' references changed to 'Trap'

4 years agofix proof_datamerger (see 216#c56)
Tobias Platen [Fri, 5 Jun 2020 19:18:46 +0000 (21:18 +0200)]
fix proof_datamerger (see 216#c56)

4 years agoupdate comments
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:45:27 +0000 (16:45 +0100)]
update comments

4 years agoadd comments and start of elaborate
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:33:05 +0000 (16:33 +0100)]
add comments and start of elaborate

4 years agomore comments
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:21:05 +0000 (16:21 +0100)]
more comments

4 years agomore comments
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:19:50 +0000 (16:19 +0100)]
more comments

4 years agoa_i not b_in
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:16:03 +0000 (16:16 +0100)]
a_i not b_in

4 years agoadd comments
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:14:21 +0000 (16:14 +0100)]
add comments

4 years agoexperimenting with CR, not quite right
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 12:51:52 +0000 (13:51 +0100)]
experimenting with CR, not quite right

4 years agoMade small changes to fu/trap/main_stage to bring nmigen into line with
colepoirier [Fri, 5 Jun 2020 14:12:26 +0000 (07:12 -0700)]
Made small changes to fu/trap/main_stage to bring nmigen into line with
microwatt VHDL

4 years agoimplement init function of DualPortSplitter
Tobias Platen [Fri, 5 Jun 2020 14:01:41 +0000 (16:01 +0200)]
implement init function of DualPortSplitter

4 years agouncomment rtlil.convert in test_l0_cache that causes runtime error
Tobias Platen [Fri, 5 Jun 2020 13:13:26 +0000 (15:13 +0200)]
uncomment rtlil.convert in test_l0_cache that causes runtime error

4 years agowhoops returning cr2 for cr3 regspec map
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 12:40:19 +0000 (13:40 +0100)]
whoops returning cr2 for cr3 regspec map

4 years agoname regfile ports by name not numerical position
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 11:36:56 +0000 (12:36 +0100)]
name regfile ports by name not numerical position

4 years agowhoops connecting up CR in wrong order. fixing with list sort
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 11:13:10 +0000 (12:13 +0100)]
whoops connecting up CR in wrong order.  fixing with list sort

4 years agofix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 10:45:34 +0000 (11:45 +0100)]
fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)

4 years agoadd TODO for MFSPR/MTSPR
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 04:01:11 +0000 (05:01 +0100)]
add TODO for MFSPR/MTSPR

4 years agorefer to srr0/1 not a/b
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 03:53:52 +0000 (04:53 +0100)]
refer to srr0/1 not a/b

4 years agoadd msr_copy function and use it in OP_TRAP, OP_RFID and OP_SC
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 03:51:09 +0000 (04:51 +0100)]
add msr_copy function and use it in OP_TRAP, OP_RFID and OP_SC

4 years agoset SRR0 in OP_SC
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 03:41:05 +0000 (04:41 +0100)]
set SRR0 in OP_SC

4 years agoadd OP_RFID SRR0/SRR1 in PowerDecode2
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 03:37:41 +0000 (04:37 +0100)]
add OP_RFID SRR0/SRR1 in PowerDecode2

4 years agoUse a_i and b_i convenience variables instead of a and b registers in
colepoirier [Thu, 4 Jun 2020 22:37:19 +0000 (15:37 -0700)]
Use a_i and b_i convenience variables instead of a and b registers in
fu/trap/main_stage

4 years agotesting CRs after writing: not in the right bit-order
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:53:20 +0000 (21:53 +0100)]
testing CRs after writing: not in the right bit-order

4 years agoremove unneeded code
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:34:00 +0000 (21:34 +0100)]
remove unneeded code

4 years agouse common TestCase class in logical
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:01:11 +0000 (21:01 +0100)]
use common TestCase class in logical

4 years agoadd branch test case to core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:00:58 +0000 (21:00 +0100)]
add branch test case to core

4 years agono global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:58:01 +0000 (20:58 +0100)]
no global variables in test suites

4 years agosigh. because POWER. CR index inversion
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:54:16 +0000 (20:54 +0100)]
sigh.  because POWER. CR index inversion

4 years agosigh. weirdness involving bit-inversion, inconsistency on mfcr and isel
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:49:32 +0000 (20:49 +0100)]
sigh.  weirdness involving bit-inversion, inconsistency on mfcr and isel

4 years agono global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:20:22 +0000 (20:20 +0100)]
no global variables in test suites

4 years agoadd ShiftRot test case (works only because CRs are not tested)
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:18:18 +0000 (20:18 +0100)]
add ShiftRot test case (works only because CRs are not tested)

4 years agoadd both logical and ALU test core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:17:12 +0000 (20:17 +0100)]
add both logical and ALU test core

4 years agono global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:13:40 +0000 (20:13 +0100)]
no global variables in test suites

4 years agono global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:12:11 +0000 (20:12 +0100)]
no global variables in test suites

4 years agono global variables in test suites
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:10:37 +0000 (20:10 +0100)]
no global variables in test suites

4 years agowhoops, docstring indentation
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:05:33 +0000 (20:05 +0100)]
whoops, docstring indentation

4 years agoadd docstrings for read/write port connection
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 18:54:36 +0000 (19:54 +0100)]
add docstrings for read/write port connection

4 years agomove core code into separate functions, for clarity
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 18:50:46 +0000 (19:50 +0100)]
move core code into separate functions, for clarity

4 years agoreduce amount of code in SelectableInt
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:57:36 +0000 (18:57 +0100)]
reduce amount of code in SelectableInt

4 years agooops forgot to switch write-enable off
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:53:13 +0000 (18:53 +0100)]
oops forgot to switch write-enable off

4 years agocomment clarify on core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:48:46 +0000 (18:48 +0100)]
comment clarify on core

4 years agoinitialise XER from simulation
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:45:31 +0000 (18:45 +0100)]
initialise XER from simulation

4 years agomessing with valid/busy signals in core test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:27:27 +0000 (18:27 +0100)]
messing with valid/busy signals in core test

4 years agoadd extra argument (not used) to regfile.py
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:27:03 +0000 (18:27 +0100)]
add extra argument (not used) to regfile.py

4 years agohmmm sync-delay wport write and wen
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 17:26:07 +0000 (18:26 +0100)]
hmmm sync-delay wport write and wen

4 years agowhitespace
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:52:21 +0000 (17:52 +0100)]
whitespace

4 years agotest actual reg values being produced in core test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:45:41 +0000 (17:45 +0100)]
test actual reg values being produced in core test

4 years agouse common TestCase in branch
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:34:37 +0000 (17:34 +0100)]
use common TestCase in branch

4 years agouse common TestCase in shift_rot
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:32:56 +0000 (17:32 +0100)]
use common TestCase in shift_rot

4 years agouse common TestCase in alu
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:31:47 +0000 (17:31 +0100)]
use common TestCase in alu

4 years agomove TestCase to common location
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:29:00 +0000 (17:29 +0100)]
move TestCase to common location

4 years agomove reg setup to earlier in test
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:28:46 +0000 (17:28 +0100)]
move reg setup to earlier in test

4 years agocomment out wrflag as it should already be in the fu.wr.rel logic
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 15:09:20 +0000 (16:09 +0100)]
comment out wrflag as it should already be in the fu.wr.rel logic

4 years agotest against Logical (hard-coded change)
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:30:44 +0000 (14:30 +0100)]
test against Logical (hard-coded change)

4 years agoadd first cut at test core
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:23:26 +0000 (14:23 +0100)]
add first cut at test core

4 years agosync onto fu.go_wr_i otherwise a loop occurs
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:21:42 +0000 (14:21 +0100)]
sync onto fu.go_wr_i otherwise a loop occurs

4 years agoadd rdmask and issue/busy setting
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:06:42 +0000 (14:06 +0100)]
add rdmask and issue/busy setting

4 years agoremove unneeded imports
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:51:01 +0000 (13:51 +0100)]
remove unneeded imports

4 years agouse copy of FHDLTestCase
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:48:17 +0000 (13:48 +0100)]
use copy of FHDLTestCase

4 years agoconnect up write-ports from Regfiles to FUs
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:03:04 +0000 (13:03 +0100)]
connect up write-ports from Regfiles to FUs

4 years agodocstring for AllFunctionUnits
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:54:09 +0000 (12:54 +0100)]
docstring for AllFunctionUnits

4 years agomissing a fastregs write-port
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:53:41 +0000 (12:53 +0100)]
missing a fastregs write-port

4 years agoupdate docstring on simple/core.py
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:31:38 +0000 (12:31 +0100)]
update docstring on simple/core.py

4 years agomove regfile/spec organiser to separate function
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:27:10 +0000 (12:27 +0100)]
move regfile/spec organiser to separate function

4 years agomention convenience variables
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:03:55 +0000 (12:03 +0100)]
mention convenience variables

4 years agorename trap to use convenience variables
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 10:58:49 +0000 (11:58 +0100)]
rename trap to use convenience variables

4 years agoUndo damage done by deleting VHDL microwatt comments,
colepoirier [Thu, 4 Jun 2020 00:22:32 +0000 (17:22 -0700)]
Undo damage done by deleting VHDL microwatt comments,
merge resolution deletion of convenience variables in
fu/trap/main_stage

4 years agocollate fu-enable signals
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:24:20 +0000 (01:24 +0100)]
collate fu-enable signals

4 years agoconnect up Function Unit operand subsets
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:18:34 +0000 (01:18 +0100)]
connect up Function Unit operand subsets