| 2020-07-01 |
Luke Kenneth Casson... | add in trap compunit
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commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | add rfid and td/tw trap test
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commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | continue debugging trap pipeline
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commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | debugging trap pipeline
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commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | start running trap unit test, fixing errors
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commit | commitdiff | tree |
| 2020-06-30 |
Luke Kenneth Casson... | add lte ltu for use by twi and other trap functions
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commit | commitdiff | tree |
| 2020-06-30 |
Luke Kenneth Casson... | add in pseudocode keyword into mdwn isa files
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commit | commitdiff | tree |
| 2020-06-30 |
Luke Kenneth Casson... | code-morph on div pipeline
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | add README for fu directory
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | use correct ALUHelpers in div test
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | sort out syntax errors in div
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | first unit test for div
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | update submodule to fix div bug
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | add ignore for parsetab.py
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | add autogenerated do not commit comment
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | update submodule to div overflow
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | separate out divide by zero cases
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | update OV and OV32 ISACaller flags if overflow occurs
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | attempting to add overflow setting in ISACaller
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | whoops, hex parser digits are in multiples of 4 bits
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commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | fetch instructions from bare wishbone fetch unit
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add cached fetch unit pass-through args
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | need args to WishboneArbiter, match data width size
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | read from instruction memory using FetchUnitInterface
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add Config Fetch interface and quick unit test
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add test instruction memory
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add readonly option to TestMemory
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | expand instruction bus width to 64 bit, start on a...
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | parameterise minerva i-cache
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | got Pi2LSUI FSM working
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | sram address do not cut by LSBs
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | new Pi2LSUI working, using PortInterfaceBase
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | start new version of Pi2LSUI based on PortInterfaceBase
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | pass addr/mask through to PortInterfaceBase rd/wr addr
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | cleanup (remove unneeded imports)
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | more code-shuffle for TestMemoryPortInterface
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | more code-shuffle for TestMemoryPortInterface
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | minor cleanup, put get/set rdport/wrport into function
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | merge LDSTPort into TestMemoryPortInterface
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | use PortInterface connect_port
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | use PortInterface connect_port
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commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | attempt to get Pi2LSUI FSM working
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | only activate ld_in_progress if addr is ok
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | make Memory accessible via TestSRAMBareLoadStoreUnit
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | increase (double) address width in TstL0CacheBuffer
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | increase (double) address width in TstL0CacheBuffer
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | unit test in l0_cache to connect to testpi and test_bare_wb
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | make PortInterface modules consistent with same API
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | use ConfigMemoryPortInterface in TstL0CacheBuffer
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | fix TestMemLoadStoreUnit, it required a FSM to monitor...
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | add wishbone Pi2LSUI test
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commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | reconfigureable PortInterface testing now possible
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | name issue in Pi2LSUI
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whitespace and imports
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | slight reorg on test_pi2ls.py
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | correct address in pi2ls
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | oops forgot to initialise base class of TestMemLoadStoreUnit
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add in LenExpand shift/mask
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add quick test showing Pi2LSUI not quite reading/writing to
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | remove extraneous yields
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | set address ok and fix unit test to check it properly
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add pi.busy_o connection, increase to 64 bit
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | unit test broken is ok :)
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | set pi.ld.ok to 1 if pi.is_ld_i is set
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | load/store unit test needed to wait for busy_o
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | clean up output from BareLoadStoreUnit
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | halve the test memory size again
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | shrink test memory size down to only 64 words
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | investigating why write-enable not getting passed through
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whoops forgot to call parent elaborate
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add test of SRAM through wishbone bus
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | code-morph which redirects lsmem unit test through...
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add a test SRAM that lives behind a minerva LoadStoreUnitInt...
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | dynamically specify wishbone layout (no longer hardcoded...
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add reconfigureable Load/Store class
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commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | extra parameterification of minerva LoadStoreUnits
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | allow Pi2LSUI to accept incoming PortInterface and...
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add extra parameter, mask_wid, to TestMemLoadStoreUnit
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | start connecting up Pi2LSUI
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add LenExpand module, tidyup on docstring
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add beginnings of Pi2LSUI
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add nmigen-soc to dependencies
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add attempt at mapping between PortInterface and LoadStoreUn...
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | rename LoadStoreInterface signals to include _i and...
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commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2020-06-24 |
Luke Kenneth Casson... | move comments to minerva LoadStoreInterface
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commit | commitdiff | tree |
| 2020-06-24 |
Luke Kenneth Casson... | import minerva and use LoadStoreUnitInterface
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commit | commitdiff | tree |
| 2020-06-23 |
Luke Kenneth Casson... | annoying error in latest nmigen
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commit | commitdiff | tree |
| 2020-06-23 |
Luke Kenneth Casson... | TstL0CacheBuffer returns array of ports differently now
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | remove unused module
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | simplified L0CacheBuffer down to a "PortInterface Arbiter"
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | add TestMemoryPortInterface class which is designed...
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | comments for LDST CompUnit test
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | enable byte-reverse in CompLDSTUnit test
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | remove CompLDSTOpSubset, replace with just data_len.
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commit | commitdiff | tree |
| 2020-06-22 |
Luke Kenneth Casson... | move BE/LE byte-reverse into LDSTCompUnit
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commit | commitdiff | tree |
| 2020-06-20 |
Luke Kenneth Casson... | expand Memory width to 64 and granularity to 16 in...
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commit | commitdiff | tree |
| 2020-06-20 |
Luke Kenneth Casson... | add asserts to check data output is correct
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commit | commitdiff | tree |
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