| 2021-02-21 |
Luke Kenneth Casson... | comment for where SVSTATE FSM should go
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | add CR out vector detection to PowerDecoder2 no_out_vec
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | move execute_fsm to separate function in TestIssuer
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | move fetch_fsm to separate function in TestIssuer
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | add JTAG enable/disable of 4k SRAMs
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | add comments for Mode field in SVP64Asm
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | comments in SVP64RMFields
|
commit | commitdiff | tree |
| 2021-02-21 |
Luke Kenneth Casson... | create SVP64CROffs consts for when SVP64 Vector-of...
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | comments on sv.add. Rc=1 unit test
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add in Vectorised CRs when Rc=1 into ISACaller
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add CR1 to DecodeCRIn/Out
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add some debug checking to get_pdecode_cr_out
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add crossreference to bug #603
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add more debug output to get_pdecode_cr_out
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | start on CRs in SVP64 mode
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | fix SVP64Asm Rc=1 assembly
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add black-box attribute to 4k SRAM cell
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | increment CRs based on srcstep, see what happens
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add litex wishbone interconnect to 4x 4k SRAMs
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add option for QTY 4x 4k SRAM blocks (not added yet...
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add Wishbone-wrapped SPBlock_512W64B8W
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | whoops set ROM to none by mistake
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | whoops spelling error
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | add (unused) code for writing out SVSTATE in TestIssuer
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | correct arguments, set microwatt_mmu=True, pass in...
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | minor whitespace cleanup
|
commit | commitdiff | tree |
| 2021-02-20 |
Luke Kenneth Casson... | remove massive code-duplication, move simple "self...
|
commit | commitdiff | tree |
| 2021-02-17 |
Luke Kenneth Casson... | declare blank classes SPEC and EXTRA2 to add MSB-to...
|
commit | commitdiff | tree |
| 2021-02-17 |
Luke Kenneth Casson... | fix reg read/write in ISACaller, PowerDecoder2 handles...
|
commit | commitdiff | tree |
| 2021-02-16 |
Luke Kenneth Casson... | ordering wrong on svstate in ISACaller
|
commit | commitdiff | tree |
| 2021-02-16 |
Luke Kenneth Casson... | adapt botchify so it can be used for 31- or 15- etc...
|
commit | commitdiff | tree |
| 2021-02-16 |
Luke Kenneth Casson... | add indicator to PowerDecoder2 when no outputs are...
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add comments to TestIssuer
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add srcstep onto Vectorised GPRs in PowerDecoder2
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add TestRunner comments
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add Regfiles comments
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add SVSTATE reading to TestIssuer
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add SVSTATE to CoreState
|
commit | commitdiff | tree |
| 2021-02-14 |
Luke Kenneth Casson... | add extra FSM explanatory comments to TestIssuer
|
commit | commitdiff | tree |
| 2021-02-13 |
Luke Kenneth Casson... | use function for getting instruction from 32/64 bit...
|
commit | commitdiff | tree |
| 2021-02-13 |
Luke Kenneth Casson... | update svp64 unit test comments
|
commit | commitdiff | tree |
| 2021-02-13 |
Luke Kenneth Casson... | add SVP64 TestIssuer separate unit test
|
commit | commitdiff | tree |
| 2021-02-13 |
Luke Kenneth Casson... | split out TestRunner into separate module
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | add one SVP64 ALU test case to get started
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | add SVSTATE to TestCase infrastructure for use in TestIssuer
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | add skip of instruction if SVSTATE.VL=0 in ISACaller
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | validate all registers to make sure no damage occurs...
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | add srcstep and correct PC-advancing during Sub-PC...
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | comments
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | add in SVSTATE.srcstep update, loop from 0 to VL-1
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | allow PC to update by 8 in SVP64 mode
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | fix setting of SVSTATE.VL and MVL
|
commit | commitdiff | tree |
| 2021-02-12 |
Luke Kenneth Casson... | add in SVSTATE to ISACaller, not used, just passed in
|
commit | commitdiff | tree |
| 2021-02-11 |
Luke Kenneth Casson... | comments in TestIssuer for SVP64PrefixDecoder
|
commit | commitdiff | tree |
| 2021-02-10 |
Luke Kenneth Casson... | add svp64 reg decode detection to ISACaller output
|
commit | commitdiff | tree |
| 2021-02-10 |
Luke Kenneth Casson... | starting to add SVP64 register EXTRA-read and isvec...
|
commit | commitdiff | tree |
| 2021-02-10 |
Luke Kenneth Casson... | comment update
|
commit | commitdiff | tree |
| 2021-02-03 |
Luke Kenneth Casson... | nope - need it to be zero if not identified as svp64
|
commit | commitdiff | tree |
| 2021-02-03 |
Luke Kenneth Casson... | actually no need to mux in the svp64_rm, just the id...
|
commit | commitdiff | tree |
| 2021-02-03 |
Luke Kenneth Casson... | add SVP64PowerDecoder, extracts svp64 remap if correctly...
|
commit | commitdiff | tree |
| 2021-02-01 |
Luke Kenneth Casson... | ISACaller, in svp64 mode, read the next 32 bits when...
|
commit | commitdiff | tree |
| 2021-02-01 |
Luke Kenneth Casson... | sort out SelectableInt bit-ordering for identifying...
|
commit | commitdiff | tree |
| 2021-02-01 |
Luke Kenneth Casson... | construct the assembly-code prefix and base v3.0B in...
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | start an ISACaller SVP64 unit test
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | test SVP64 major opcode, start checking if it is EXT001...
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | adjusting ISACaller unit test to use ISACaller.setup_one()
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | fix ISACaller unit test
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | SVP64 Remap Fields structures for ISACaller
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | remove sv_rm from PowerDecoder register decoders
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | add SVSTATE SPR sub-field accessor class to ISACaller
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | move SVP64 Extra reg decoding into main PowerDecoder...
|
commit | commitdiff | tree |
| 2021-01-31 |
Luke Kenneth Casson... | update submodule
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | move CR in/out SVP64 EXTRA decoders into PowerDecoder
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | add SVP64 CR out extending to 7-bit in PowerDecoder2
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | add SVP64 CR EXTRA field-extension, from 3-bit to 7...
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | extend CR registers in Decode2ToExecute1Type to 7 bit
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | add SVP64CRExtra class to PowerDecoder2, turns 3-bit...
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | split out SVEXTRA field selection/decoding into separate...
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | whoops update PowerDecoder2 svp64 comments, reg sizes...
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | add SVP64 EXTRA decoding to RB, RC and RT (out) in...
|
commit | commitdiff | tree |
| 2021-01-30 |
Luke Kenneth Casson... | add first SVP64 7-bit register context decoder to PowerDecoder2
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | add SVP64RM record to PowerDecoder2
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | increase register number sizes from 5 to 7
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | syntax corrections, also size of maxvl was wrong
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | add SVP64 RM (Remap) Record
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | adjust SVP64RM class to output more PowerDecoder-friendly...
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | adjust how register copy/setup is done in PowerDecoder2
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | add SV etype/ptype to power decoder
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | whoops syntax error. submodule update
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | start adding svp64 enums
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | use new svp64-augmented csv reader in PowerDecoder
|
commit | commitdiff | tree |
| 2021-01-29 |
Luke Kenneth Casson... | whoops missed out "+" on explicit license listing
|
commit | commitdiff | tree |
| 2021-01-28 |
Luke Kenneth Casson... | add SVSTATE to StateRegs
|
commit | commitdiff | tree |
| 2021-01-28 |
Luke Kenneth Casson... | add SVState SPR Record, SVSTATERec
|
commit | commitdiff | tree |
| 2021-01-28 |
Luke Kenneth Casson... | add svp64 CR field identification for EXTRA2/3 decoding
|
commit | commitdiff | tree |
| 2021-01-28 |
Luke Kenneth Casson... | move svp64 reg-decode function to more appropriate...
|
commit | commitdiff | tree |
| 2021-01-28 |
Luke Kenneth Casson... | provide "merger" of SVP64 RM info into v3.0B CSV files
|
commit | commitdiff | tree |
| 2021-01-27 |
Luke Kenneth Casson... | move SVP64RM CSV class to new module
|
commit | commitdiff | tree |
| 2021-01-27 |
Luke Kenneth Casson... | whitespace and shortening of SPR MMU redirection in...
|
commit | commitdiff | tree |
| next |
projects / soc.git / search