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soc.git
2021-05-13 Luke Kenneth... update comments in issuer.py regarding a 4th FSM commit | commitdiff | tree
2021-05-13 Luke Kenneth... yet more debug log stuff for DCache, this time on Cache... commit | commitdiff | tree
2021-05-13 Luke Kenneth... fix wb_get error where data was being corrupted commit | commitdiff | tree
2021-05-13 Luke Kenneth... add read at different locations in test_ldst_pi.py commit | commitdiff | tree
2021-05-13 Luke Kenneth... add some data for MMU to actually look up commit | commitdiff | tree
2021-05-13 Luke Kenneth... ha, hilarious: swapped TLBUpdate output sizes db_out... commit | commitdiff | tree
2021-05-13 Luke Kenneth... whoops TLBIE must *clear* the valid bit not set it... commit | commitdiff | tree
2021-05-13 Luke Kenneth... more debug Display in dcache.py commit | commitdiff | tree
2021-05-13 Luke Kenneth... putting in a lot more debug print statements in DCache... commit | commitdiff | tree
2021-05-12 Luke Kenneth... add dcache tlb / pte test commit | commitdiff | tree
2021-05-12 Luke Kenneth... set m_out.load from ldst_r(egister) in LoadStore1 commit | commitdiff | tree
2021-05-12 Luke Kenneth... move dcache unit test to separate test_dcache.py commit | commitdiff | tree
2021-05-12 Luke Kenneth... experimentation with MMU-enabled LoadStore1 through... commit | commitdiff | tree
2021-05-12 Luke Kenneth... add debug info, update comments, disable dcache in... commit | commitdiff | tree
2021-05-12 Luke Kenneth... start doing virtual memory queries via PortInterface... commit | commitdiff | tree
2021-05-12 Luke Kenneth... whoops missing default zero (no idea how) commit | commitdiff | tree
2021-05-12 Luke Kenneth... addcomments for MMU PortInterface test (how it, um... commit | commitdiff | tree
2021-05-12 Luke Kenneth... bit of a hack to get test_mmu_dcache_pi.py operational. commit | commitdiff | tree
2021-05-12 Luke Kenneth... whitespace commit | commitdiff | tree
2021-05-12 Luke Kenneth... no need for sel0 commit | commitdiff | tree
2021-05-11 Luke Kenneth... pass through MSR.PR through PortInterface, into LoadStore1 commit | commitdiff | tree
2021-05-11 Luke Kenneth... connect MSR.PR to PortInterface in LDSTCompUnit commit | commitdiff | tree
2021-05-11 Luke Kenneth... add msr_pr bit in PortInterface commit | commitdiff | tree
2021-05-11 Luke Kenneth... add MSR to LD/ST Input Record commit | commitdiff | tree
2021-05-11 Luke Kenneth... comment tidyup commit | commitdiff | tree
2021-05-11 Luke Kenneth... must also pass through instruction fault exception... commit | commitdiff | tree
2021-05-11 Luke Kenneth... whoops names changed in MMU FSM commit | commitdiff | tree
2021-05-11 Luke Kenneth... tidyup comments and remove LoadStore COMPLETE state commit | commitdiff | tree
2021-05-11 Luke Kenneth... cleanup on exception setting commit | commitdiff | tree
2021-05-11 Luke Kenneth... rename LoadStore1 data structures back to microwatt... commit | commitdiff | tree
2021-05-10 Luke Kenneth... add block for MMU activation to LoadStore1 commit | commitdiff | tree
2021-05-10 Luke Kenneth... move LoadStore1 d_validblip setting, and get MMU_LOOKUP... commit | commitdiff | tree
2021-05-10 Luke Kenneth... whoops, indentation issue on m.If/m.Else in dcache.py commit | commitdiff | tree
2021-05-10 Tobias Platenstyle-wise: use ~self.instr_fault not self.instr_fault==0 commit | commitdiff | tree
2021-05-10 Tobias PlatenLoadStore1: add rules for MMU_LOOKUP commit | commitdiff | tree
2021-05-10 Luke Kenneth... add links to set associative image, and bugreport commit | commitdiff | tree
2021-05-09 Luke Kenneth... add comments on translation of MMU_LOOKUP commit | commitdiff | tree
2021-05-09 Luke Kenneth... install MMU_LOOKUP vhdl to be translated to nmigen commit | commitdiff | tree
2021-05-09 Luke Kenneth... move (unused) ACK_WAIT code into FSM commit | commitdiff | tree
2021-05-09 Luke Kenneth... add comments in LoadStore1 commit | commitdiff | tree
2021-05-09 Luke Kenneth... remove invalid setting of d_in.valid from self.mmureq commit | commitdiff | tree
2021-05-09 Luke Kenneth... no SECOND_REQ commit | commitdiff | tree
2021-05-09 Luke Kenneth... remove SECOND_REQ commit | commitdiff | tree
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py drive output d_in.valid commit | commitdiff | tree
2021-05-09 Tobias Platenmove skeleton to elaborate commit | commitdiff | tree
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py: add skeleton for fsm commit | commitdiff | tree
2021-05-09 Luke Kenneth... add comment about LD/ST exception needs copying into... commit | commitdiff | tree
2021-05-09 Luke Kenneth... run LD/ST Exception test case for MMU commit | commitdiff | tree
2021-05-09 Luke Kenneth... add MMU bugtracker link commit | commitdiff | tree
2021-05-09 Luke Kenneth... git submodule update commit | commitdiff | tree
2021-05-09 Luke Kenneth... update code-comments commit | commitdiff | tree
2021-05-09 Luke Kenneth... add in alignment exception capture/reporting in LoadStore1 commit | commitdiff | tree
2021-05-09 Luke Kenneth... preference is to create a temp variable for comb and... commit | commitdiff | tree
2021-05-09 Luke Kenneth... add misalign flag to PortInterfaceBase commit | commitdiff | tree
2021-05-08 Luke Kenneth... LoadStore1 tidyup commit | commitdiff | tree
2021-05-08 Luke Kenneth... transferring more over to LoadStore FSM commit | commitdiff | tree
2021-05-08 Luke Kenneth... start putting state info into LoadStore1, slowly puttin... commit | commitdiff | tree
2021-05-08 Luke Kenneth... add LoadStore State enum commit | commitdiff | tree
2021-05-08 Luke Kenneth... add bugreport link to mmu commit | commitdiff | tree
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc... commit | commitdiff | tree
2021-05-07 Luke Kenneth... start setting DSISR bits but commented out commit | commitdiff | tree
2021-05-07 Luke Kenneth... update comments and docstrings commit | commitdiff | tree
2021-05-07 Luke Kenneth... whoops, import error commit | commitdiff | tree
2021-05-07 Luke Kenneth... move LoadStore1 class to soc.fu.ldst.loadstore commit | commitdiff | tree
2021-05-07 Luke Kenneth... whoops was still copying output over in CommonOutputStage commit | commitdiff | tree
2021-05-07 Luke Kenneth... how we managed to get this far without noticing that... commit | commitdiff | tree
2021-05-07 Luke Kenneth... move dsisr and dar into LoadStore1 commit | commitdiff | tree
2021-05-07 Luke Kenneth... move zero-dest-pred in Common Output Stage to not copy... commit | commitdiff | tree
2021-05-07 Luke Kenneth... whoops setup of core.sv_pred_sm/dm not indented and... commit | commitdiff | tree
2021-05-06 Luke Kenneth... whoops disabled tests agaaaaain commit | commitdiff | tree
2021-05-06 Luke Kenneth... pass relevant predicate mask bits through to Decoders... commit | commitdiff | tree
2021-05-06 Luke Kenneth... add in predicate mask bit detection when zeroing is... commit | commitdiff | tree
2021-05-06 Luke Kenneth... pass SVP64 ReMap field through to core and then on... commit | commitdiff | tree
2021-05-06 Luke Kenneth... moved exts* SVP64 unit tests to a different location commit | commitdiff | tree
2021-05-06 Jonathan Neuschäfer.gitlab-ci.yml: Increase the build timeout commit | commitdiff | tree
2021-05-06 Luke Kenneth... argh someobe falsely stated in the README that LibreSOC... commit | commitdiff | tree
2021-05-06 Luke Kenneth... if zeroing is set, put zero into input or output as... commit | commitdiff | tree
2021-05-05 Tobias Platenfix bug in mmu/fsm.py commit | commitdiff | tree
2021-05-05 Luke Kenneth... simplify README.md so that it gets submitted to pypi commit | commitdiff | tree
2021-05-05 Luke Kenneth... mark long description type as markdown commit | commitdiff | tree
2021-05-05 Luke Kenneth... update NEWS.txt commit | commitdiff | tree
2021-05-05 Luke Kenneth... add libresoc-openpower-isa to setup.py dependencies commit | commitdiff | tree
2021-05-05 Luke Kenneth... put sv_input_record_layout onto CompOpSubsetBase after all commit | commitdiff | tree
2021-05-05 Luke Kenneth... whoops wrong signal name, set exc_happened commit | commitdiff | tree
2021-05-05 Luke Kenneth... add SVP64 RM fields to ALU input record commit | commitdiff | tree
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py commit | commitdiff | tree
2021-05-04 Luke Kenneth... remove minerva debug unit (not needed) commit | commitdiff | tree
2021-05-04 Jonathan Neuschäferminerva tests: Don't import soc.minerva.csr commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Silence pywriter harder commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Trim log output commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Fix invocation of pywriter commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Clone and build power-instruction-analyzer commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Clone and build c4m-jtag commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Clone and build openpower-isa commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Install Rust and cargo commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Remove tags from nmigen-soc repo commit | commitdiff | tree
2021-05-04 Jonathan Neuschäfer.gitlab-ci.yml: Rewrite git://git.libre-riscv.org URLs... commit | commitdiff | tree
2021-05-04 Luke Kenneth... whoops disabled some test_issuer group tests commit | commitdiff | tree
2021-05-04 Luke Kenneth... add SVSTATE (SVSRR0) to TRAP pipeline commit | commitdiff | tree
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