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soc.git
2020-09-05 Luke Kenneth... move GPIO IRQ to 15 to match microwatt modifications commit | commitdiff | tree
2020-09-05 Luke Kenneth... hmmm XICS data being asserted on wb bus for too long commit | commitdiff | tree
2020-09-05 Luke Kenneth... argh missed a VHDL "&" translating to Cat commit | commitdiff | tree
2020-09-05 Luke Kenneth... reduce XICS address lookup by 2 bits commit | commitdiff | tree
2020-09-05 Luke Kenneth... MSR read in INSN_READ only occurs for 1 cycle commit | commitdiff | tree
2020-09-05 Luke Kenneth... sync on ICP eint commit | commitdiff | tree
2020-09-05 Luke Kenneth... connect XICS core irq to Decode2 eint commit | commitdiff | tree
2020-09-05 Luke Kenneth... whoops, combinatorial loop on pending_priority commit | commitdiff | tree
2020-09-05 Luke Kenneth... use stbcix in test commit | commitdiff | tree
2020-09-05 Luke Kenneth... XICS addresses in words: divide by 4 commit | commitdiff | tree
2020-09-05 Luke Kenneth... whoops, ICS in litex sim needs to be 0x1000 size region commit | commitdiff | tree
2020-09-05 Luke Kenneth... add lwzcix unit test commit | commitdiff | tree
2020-09-05 Luke Kenneth... increase wishbone address width to 29 for xics and... commit | commitdiff | tree
2020-09-05 Luke Kenneth... submodule update commit | commitdiff | tree
2020-09-05 Luke Kenneth... add simple GPIO wishbone bus to litex sim.py commit | commitdiff | tree
2020-09-05 Luke Kenneth... add stbcix and lwzcix to power_enum list commit | commitdiff | tree
2020-09-05 Luke Kenneth... add simple GPIO peripheral to verilog TestIssuer commit | commitdiff | tree
2020-09-05 Luke Kenneth... move wb read/write to separate util test library and... commit | commitdiff | tree
2020-09-05 Luke Kenneth... add simple wishbone GPIO peripheral commit | commitdiff | tree
2020-09-05 Samuel A. Falvo IIAdd unit test replicating failing proof case commit | commitdiff | tree
2020-09-04 Luke Kenneth... add sld test with RB=64 to see what happens commit | commitdiff | tree
2020-09-04 Luke Kenneth... reduce CSR data width to 8 as an experiment commit | commitdiff | tree
2020-09-04 Luke Kenneth... add UART reserved IRQ @ 0 commit | commitdiff | tree
2020-09-04 Luke Kenneth... add XICS memory regions, shrink litex CSR memmap size... commit | commitdiff | tree
2020-09-04 Luke Kenneth... adding XICS wb slave devices to litex sim commit | commitdiff | tree
2020-09-04 Luke Kenneth... bring out XICS ICS interrupt levels so that they can... commit | commitdiff | tree
2020-09-04 Luke Kenneth... adding option to include XICS external interrupts. commit | commitdiff | tree
2020-09-04 Luke Kenneth... add means to run hello_world.bin under simulation commit | commitdiff | tree
2020-09-04 Jacob Lifshayupdate to match refactored power-instruction-analyzer API commit | commitdiff | tree
2020-09-03 Samuel A. Falvo IIProvide full name and email in copyright notice. commit | commitdiff | tree
2020-09-03 Luke Kenneth... do more on dcache conversion commit | commitdiff | tree
2020-09-03 Luke Kenneth... testing microwatt 3.bin (2.bin ok) commit | commitdiff | tree
2020-09-02 Luke Kenneth... when mtocrf FXM is 0, the CR has to be set to CR7 commit | commitdiff | tree
2020-09-02 Luke Kenneth... fix bug in cmpli (and cmplw) commit | commitdiff | tree
2020-09-02 Luke Kenneth... sign-extend lhax needs 16-64, separate from lwax which... commit | commitdiff | tree
2020-09-02 Luke Kenneth... add bc ctr regression test when CTR=0 and CTR=1 commit | commitdiff | tree
2020-09-02 Luke Kenneth... update submodule commit | commitdiff | tree
2020-09-02 Luke Kenneth... bug in carry32 handling in OP_CMP commit | commitdiff | tree
2020-09-02 Luke Kenneth... add cmpl regression test (one binary, one assembly) commit | commitdiff | tree
2020-09-02 Luke Kenneth... add cmpl microwatt 1.bin test, cmpl commit | commitdiff | tree
2020-09-02 Luke Kenneth... series of extensive modifications to fix long-standing... commit | commitdiff | tree
2020-08-31 Luke Kenneth... add XER to fastregs and "construct" it in mfspr/mtspr commit | commitdiff | tree
2020-08-30 Luke Kenneth... redo OP_CMP based on microwatt. L=1 had been ignored commit | commitdiff | tree
2020-08-30 Luke Kenneth... reversal of FXM mask for one-hot selection in OP_MTCR... commit | commitdiff | tree
2020-08-30 Luke Kenneth... working on dcache.py commit | commitdiff | tree
2020-08-30 Luke Kenneth... tidyup on mul proof commit | commitdiff | tree
2020-08-30 Luke Kenneth... set mul post_stage o.ok only when needed, and fix xer_s... commit | commitdiff | tree
2020-08-30 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-30 Cole Poiriericache.py commit progress, about a third through the... commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIQualify XER_OV output in proof commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIFix test breakage in MUL proofs commit | commitdiff | tree
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza... commit | commitdiff | tree
2020-08-29 Cole Poiriermem_types add more types from common.vhdl specifially... commit | commitdiff | tree
2020-08-29 Cole Poiriermem_types.py arrange in alphabetical order for ease... commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!! commit | commitdiff | tree
2020-08-29 Cole Poiriermmu.py remove duplicate comment left over from mmu... commit | commitdiff | tree
2020-08-29 Cole Poiriericache.py initial commit of first attempt at translatio... commit | commitdiff | tree
2020-08-29 Cesar StraussMove new write_gtkw and its example to nmutil commit | commitdiff | tree
2020-08-29 Luke Kenneth... minor code-shuffle, comments commit | commitdiff | tree
2020-08-29 Luke Kenneth... slowly morphing towards using an XER bit-field selector... commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIMUL pipeline formal proofs complete, I *think*. commit | commitdiff | tree
2020-08-29 Luke Kenneth... break down XER into flags commit | commitdiff | tree
2020-08-29 Luke Kenneth... add XER read via DMI interface to sim.py commit | commitdiff | tree
2020-08-29 Luke Kenneth... add hack to get at XER through DMI interface commit | commitdiff | tree
2020-08-29 Luke Kenneth... submodule update commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIWIP: prep for 64-bit insns commit | commitdiff | tree
2020-08-29 Luke Kenneth... yep disable OE for MULH64/32 and EXTS and CNTZ commit | commitdiff | tree
2020-08-29 Luke Kenneth... investigating CR mtocrf / mfocrf commit | commitdiff | tree
2020-08-29 Luke Kenneth... add additional CR regression tests commit | commitdiff | tree
2020-08-29 Luke Kenneth... allow pseudocode numbering to decrement in for-loops commit | commitdiff | tree
2020-08-29 Luke Kenneth... add wat to write out raw binary assembled programs commit | commitdiff | tree
2020-08-29 Luke Kenneth... CR FXM becomes a full mask. commit | commitdiff | tree
2020-08-28 Cole Poirierdcache.py add first attempt at translation of dcache_tb... commit | commitdiff | tree
2020-08-27 Cole Poirierdcache.py add skeleton sim and test adapted from mmu... commit | commitdiff | tree
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-27 Cole Poirierdcache.py implement the remaining vhdl generate stateme... commit | commitdiff | tree
2020-08-27 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=476 commit | commitdiff | tree
2020-08-27 Luke Kenneth... xer so is not being passed through to CR0 commit | commitdiff | tree
2020-08-27 Luke Kenneth... really bad hack to fix simulator bug in carry handling commit | commitdiff | tree
2020-08-27 Luke Kenneth... augment addme test case to show bug #476 commit | commitdiff | tree
2020-08-27 Luke Kenneth... add addze and addme uni tests commit | commitdiff | tree
2020-08-27 Luke Kenneth... incompatibility with POWER9 on mulhw/u due to lack... commit | commitdiff | tree
2020-08-27 Luke Kenneth... overflow-enable does not occur on shift operations commit | commitdiff | tree
2020-08-27 Luke Kenneth... oink, write_cr shiftrot record width was zero (??) commit | commitdiff | tree
2020-08-27 Luke Kenneth... sorting out shift_rot to use new output stage data... commit | commitdiff | tree
2020-08-27 Luke Kenneth... need to read SO if Rc=1 commit | commitdiff | tree
2020-08-27 Luke Kenneth... reorg of SO handling related to CR0 commit | commitdiff | tree
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-26 Cole Poirierdcache.py replace subtypes/types/constant aliases with... commit | commitdiff | tree
2020-08-26 Luke Kenneth... use sub-test in logical test_pipe_caller commit | commitdiff | tree
2020-08-26 Luke Kenneth... investigating div fsm and simulator bug commit | commitdiff | tree
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py rearrange, transform classes into functions... commit | commitdiff | tree
2020-08-25 Jacob Lifshayfix broken remainder for div FSM commit | commitdiff | tree
2020-08-25 Jacob Lifshayclean up formatting commit | commitdiff | tree
2020-08-25 Luke Kenneth... although shift-rot does not alter XER.so it still needs... commit | commitdiff | tree
2020-08-25 Luke Kenneth... add way to capture CR from DMI in litex sim commit | commitdiff | tree
2020-08-25 Luke Kenneth... add CR read to DMI interface commit | commitdiff | tree
2020-08-25 Luke Kenneth... shorten using temp vars commit | commitdiff | tree
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