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add Makefile for verilog compilation
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.gitignore
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Makefile
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README.txt
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ReadMe.md
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block_memory.v
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block_memory_16kbit.v
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cpu.bmm
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cpu.py
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cpu.v
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cpu.vh
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cpu_alu.v
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cpu_decoder.py
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cpu_decoder.v
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cpu_fetch_action.py
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cpu_fetch_stage.py
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cpu_fetch_stage.v
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cpu_handle_csr.py
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cpu_handle_trap.py
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cpu_loadstore_calc.py
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cpu_memory_interface.v
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cpu_mie.py
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cpu_mip.py
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cpu_mstatus.py
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cpudefs.py
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font8x8.hex
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main.bit
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main.ucf
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main.v
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main_test.v
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pipestage.py
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regfile.py
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riscv.vh
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riscvdefs.py
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rv32.xise
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text_initial.hex
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vga.v
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vga_clock_generator.v
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vga_font_generator.v
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vga_location_generator.v
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vga_text_buffer.v
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