rename invert_a to invert_in because logical inverts RB
[soc.git] / src / soc / experiment / test / test_compalu_multi.py
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... testing if MultiCompUnit can handle no input regs ...
2020-07-21 Luke Kenneth Casso... disable cxxsim for now
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... add some CompUnit demo tests of the alu_fsm example
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-09 Cesar StraussAvoid a combinatorial loop on valid_o
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Cesar StraussCheck completion of the sub-processes
2020-06-03 Cesar StraussSimplify immediate check
2020-06-03 Cesar StraussPreliminary check of the alu protocol
2020-06-03 Cesar StraussPass along the operand, in the cycle in which go is...
2020-06-02 Cesar StraussAllow at least one operand to be fetched
2020-06-02 Cesar StraussHold rdmaskn active during the busy_o cycle
2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
2020-05-31 Luke Kenneth Casso... add comments for MultiCompUnit parallel test
2020-05-31 Luke Kenneth Casso... remove unneeded imports
2020-05-31 Luke Kenneth Casso... split out compalu unit tests to separate module (gettin...