| 2021-10-08 |
Luke Kenneth Casso... | whoops missed one function which should be a yield... |
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| 2021-10-08 |
Luke Kenneth Casso... | use yield from on StateRunners |
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| 2021-10-08 |
Luke Kenneth Casso... | add comments, remove unneeded code |
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| 2021-10-08 |
Luke Kenneth Casso... | move pc_i and svstate_i to HDLRunner |
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| 2021-10-08 |
klehman | add end_test, minor cleanup, added hdlrun.cleanup(... |
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| 2021-10-08 |
klehman | moved pc_i and sv_state to constructor, remove hdl_stat... |
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| 2021-10-08 |
klehman | change over run_hdl_state to TestRunner class |
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| 2021-10-08 |
Luke Kenneth Casso... | add dummy call to simrun and end_test() |
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| 2021-10-08 |
Luke Kenneth Casso... | code-comments and dummy functions |
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| 2021-10-08 |
Luke Kenneth Casso... | move contents of run_sim_state into SimRunner run_test... |
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| 2021-10-08 |
Luke Kenneth Casso... | add a SimRunner prepare_for_test and run_test function |
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| 2021-09-25 |
Las Safin | Merge remote-tracking branch 'upstream/master' into pr |
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| 2021-09-25 |
klehman | start of HDLRunner |
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| 2021-09-24 |
Luke Kenneth Casso... | create initial SimRunner |
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| 2021-09-23 |
Luke Kenneth Casso... | move pc_i and svstate_i inside if self.run_hdl |
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| 2021-09-23 |
Luke Kenneth Casso... | more comments |
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| 2021-09-23 |
Luke Kenneth Casso... | add in a stack of comments for identifying match-points... |
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| 2021-09-23 |
Luke Kenneth Casso... | add option to run ISACaller Sim (or not) |
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| 2021-09-23 |
Luke Kenneth Casso... | add a new run_hdl parameter to TestRunner |
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| 2021-09-22 |
Luke Kenneth Casso... | completely borked python segfault, workaround to copy... |
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| 2021-09-22 |
Luke Kenneth Casso... | add test of expected results against last sim state |
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| 2021-09-22 |
Luke Kenneth Casso... | whoops broken run_sim_state function |
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| 2021-09-22 |
Luke Kenneth Casso... | split out HDL from Simulator into separate functions |
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| 2021-09-22 |
Luke Kenneth Casso... | split out HDL test from Simulator test, |
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| 2021-09-22 |
Luke Kenneth Casso... | alter setup_tst_memory to take a test.mem rather than... |
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| 2021-09-21 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-09-21 |
klehman | changed test_runner to use state mem compare |
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| 2021-09-17 |
Luke Kenneth Casso... | update comments |
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| 2021-09-08 |
Cesar Strauss | Monitor the exception input to PowerDecoder2 |
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| 2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
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| 2021-08-16 |
Cesar Strauss | Adjust PortInterface traces according to MMU option |
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| 2021-08-01 |
Jonathan Neuschäfer | soc.simple.test: Rename setup_test_memory to avoid... |
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| 2021-07-15 |
Luke Kenneth Casso... | update TestRunner, SVSTATE is now a class that inherits... |
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| 2021-07-14 |
Luke Kenneth Casso... | update SVSTATE to 64 bit length (fortunately very easy) |
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| 2021-07-12 |
Luke Kenneth Casso... | use standard create_pdecode in TestRunner |
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| 2021-07-11 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-07-10 |
Cesar Strauss | Show some usage of PortInterface in action |
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| 2021-05-22 |
Cesar Strauss | Move the reset code outside of the sub-test |
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| 2021-05-07 |
Luke Kenneth Casso... | how we managed to get this far without noticing that... |
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| 2021-05-01 |
Luke Kenneth Casso... | send a DMI RESET at the end of the test. |
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| 2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
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| 2021-04-30 |
Luke Kenneth Casso... | add basic test_issuer_mmu.py |
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| 2021-04-30 |
Luke Kenneth Casso... | add option to use new mmu_cache_wb ConfigMemoryPortInte... |
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| 2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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| 2021-04-03 |
Cesar Strauss | Allow the Simulator to handle back-to-back signaling... |
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| 2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
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| 2021-03-30 |
Luke Kenneth Casso... | use port name for INT regfile to match up with test_run... |
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| 2021-03-30 |
Cesar Strauss | Memory port seems to have been renamed |
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| 2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
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| 2021-03-28 |
Luke Kenneth Casso... | reduce number of regfile ports |
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| 2021-03-22 |
Cesar Strauss | Add traces for the new FSM and integer predicate decoding |
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| 2021-03-09 |
Cesar Strauss | Add some extra debug traces to the GTKWave document |
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| 2021-03-09 |
Cesar Strauss | Create a new signal for the Simulator to wait on |
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| 2021-03-08 |
Luke Kenneth Casso... | add option in TestRunner to disable svp64 via commandli... |
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| 2021-03-03 |
Luke Kenneth Casso... | set SVSTATE in TestRunner using new TestIssuer.svstate_i |
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| 2021-03-03 |
Luke Kenneth Casso... | add svstate_i to TestIssuer which mirrors pc_i |
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| 2021-02-27 |
Cesar Strauss | Add traces for the new FSM |
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| 2021-02-24 |
Tobias Platen | test_runner.py: add needed imports |
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| 2021-02-21 |
Cesar Strauss | Hide the register augmentation traces by default |
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| 2021-02-20 |
Luke Kenneth Casso... | whoops set ROM to none by mistake |
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| 2021-02-20 |
Luke Kenneth Casso... | remove massive code-duplication, move simple "self... |
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| 2021-02-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-02-17 |
Tobias Platen | add wishbone signals to gtkwave output |
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| 2021-02-17 |
Cesar Strauss | Add the SVSTATE traces to GTKWave to allow debugging... |
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| 2021-02-17 |
Cesar Strauss | Initialize the core SVSTATE from the corresponding... |
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| 2021-02-17 |
Cesar Strauss | Revert "Setup SVSTATE, from the test settings, at the... |
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| 2021-02-17 |
Cesar Strauss | Add traces to debug SVP64 prefix decoding issues |
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| 2021-02-17 |
Cesar Strauss | Setup SVSTATE, from the test settings, at the start |
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| 2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
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| 2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-02-14 |
Cesar Strauss | Show traces for the register numbers of the current... |
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| 2021-02-14 |
Luke Kenneth Casso... | add TestRunner comments |
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| 2021-02-13 |
Luke Kenneth Casso... | split out TestRunner into separate module |
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projects / soc.git / history