2021-03-02 |
Luke Kenneth Casso... | sort out SPR setting in MMU |
tree | commitdiff |
2021-02-27 |
Cesar Strauss | Add traces for the new FSM |
tree | commitdiff |
2021-02-24 |
Tobias Platen | test_runner.py: add needed imports |
tree | commitdiff |
2021-02-23 |
Tobias Platen | deduplicate |
tree | commitdiff |
2021-02-22 |
Luke Kenneth Casso... | whoops |
tree | commitdiff |
2021-02-22 |
Luke Kenneth Casso... | moving PC-setting (NIA) out of execute_fsm in TestIssuer |
tree | commitdiff |
2021-02-21 |
Cesar Strauss | Hide the register augmentation traces by default |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | move fetch_fsm to separate function in TestIssuer |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | add JTAG enable/disable of 4k SRAMs |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | whoops set ROM to none by mistake |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | remove massive code-duplication, move simple "self... |
tree | commitdiff |
2021-02-20 |
Tobias Platen | add rom debugger |
tree | commitdiff |
2021-02-20 |
Tobias Platen | add mmu rom testcase |
tree | commitdiff |
2021-02-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-17 |
Tobias Platen | add wishbone signals to gtkwave output |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Add the SVSTATE traces to GTKWave to allow debugging... |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Initialize the core SVSTATE from the corresponding... |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Revert "Setup SVSTATE, from the test settings, at the... |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Add traces to debug SVP64 prefix decoding issues |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Setup SVSTATE, from the test settings, at the start |
tree | commitdiff |
2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
tree | commitdiff |
2021-02-15 |
Cesar Strauss | Simplify obtaining the PC from the register file |
tree | commitdiff |
2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-14 |
Cesar Strauss | Show traces for the register numbers of the current... |
tree | commitdiff |
2021-02-14 |
Luke Kenneth Casso... | add TestRunner comments |
tree | commitdiff |
2021-02-13 |
Cesar Strauss | Check the PC value at the end of each instruction |
tree | commitdiff |
2021-02-13 |
Luke Kenneth Casso... | add SVP64 TestIssuer separate unit test |
tree | commitdiff |
2021-02-13 |
Luke Kenneth Casso... | split out TestRunner into separate module |
tree | commitdiff |
2021-02-12 |
Luke Kenneth Casso... | add SVSTATE to TestCase infrastructure for use in TestI... |
tree | commitdiff |
2021-02-06 |
Cesar Strauss | Fix whitespace |
tree | commitdiff |
2021-02-06 |
Cesar Strauss | Extract the fetch FSM out from the main FSM |
tree | commitdiff |
2021-02-04 |
Tobias Platen | src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave |
tree | commitdiff |
2021-02-01 |
Tobias Platen | extending the GTKWave document in test_issuer when... |
tree | commitdiff |
2021-02-01 |
Cesar Strauss | Add GTKWave document to test_issuer |
tree | commitdiff |
2021-01-18 |
Tobias Platen | uncomment #FIXME in unit_test |
tree | commitdiff |
2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
tree | commitdiff |
2021-01-08 |
Tobias Platen | fix broken testcase for simple core |
tree | commitdiff |
2020-10-16 |
Luke Kenneth Casso... | re-enable tests |
tree | commitdiff |
2020-10-16 |
Luke Kenneth Casso... | manually run coresync clock for test issuer |
tree | commitdiff |
2020-10-16 |
Luke Kenneth Casso... | set defaults in pspec |
tree | commitdiff |
2020-10-01 |
Luke Kenneth Casso... | create dummy PLL block, connect up to core and clock... |
tree | commitdiff |
2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
tree | commitdiff |
2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
tree | commitdiff |
2020-09-08 |
Luke Kenneth Casso... | add cxxsim option |
tree | commitdiff |
2020-08-30 |
Luke Kenneth Casso... | reversal of FXM mask for one-hot selection in OP_MTCR... |
tree | commitdiff |
2020-08-29 |
Luke Kenneth Casso... | add hack to get at XER through DMI interface |
tree | commitdiff |
2020-08-27 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-27 |
Luke Kenneth Casso... | overflow-enable does not occur on shift operations |
tree | commitdiff |
2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
tree | commitdiff |
2020-08-24 |
Luke Kenneth Casso... | add isel CR tests to run on qemu (confirmed working) |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | get litex sim enabled with 32-bit wishbone bus |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | attempting to track down bug in litex bios memtest |
tree | commitdiff |
2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
tree | commitdiff |
2020-08-14 |
Luke Kenneth Casso... | sync up the core decode-execute state, |
tree | commitdiff |
2020-08-14 |
Luke Kenneth Casso... | move instruction decoder out of core |
tree | commitdiff |
2020-08-14 |
Luke Kenneth Casso... | sort out instruction stop/cancel when adding a new... |
tree | commitdiff |
2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
tree | commitdiff |
2020-08-09 |
Luke Kenneth Casso... | add logical test issuer case |
tree | commitdiff |
2020-08-05 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-05 |
Luke Kenneth Casso... | add div test cases into test_issuer.py |
tree | commitdiff |
2020-08-03 |
Luke Kenneth Casso... | add quick demo/test of reading DMI reg 9 |
tree | commitdiff |
2020-08-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-08-03 |
Luke Kenneth Casso... | change over to DMI debug start/stop interface |
tree | commitdiff |
2020-07-29 |
Jacob Lifshay | add __init__.py to all source directories |
tree | commitdiff |
2020-07-29 |
Jacob Lifshay | format some tests |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | add nop test cases |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | activate some of new accumulator-based tests in test_issuer |
tree | commitdiff |
2020-07-23 |
Luke Kenneth Casso... | support 32-bit mem width setting |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | format code |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | explicitly set up a pc_i_ok signal in test_microwatt.py |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | update to expose signals at top-level of issuer |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | add DivTestCase to test_issuer.py (commented out for... |
tree | commitdiff |
2020-07-12 |
Luke Kenneth Casso... | add OP_ATTN test back in |
tree | commitdiff |
2020-07-12 |
Luke Kenneth Casso... | msb of instruction causing sign-overflow |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | fix spr setting, set endianness |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | more setting bigendian |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | add bigendian mode to helloworld test |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | resolving bigendian/littleendian modes in qemu sim |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | resolving old and new behaviour for lookup of SPRs |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | resolving old and new behaviour for lookup of SPRs |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | adding in ALU test back in, debugging SPR setup |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | sorting out setting of XER |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | got test_issuer operational on one unit test |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | stashing current state of investigation whilst looking... |
tree | commitdiff |
2020-07-08 |
Luke Kenneth Casso... | copy binary loaded from disk into data memory as well |
tree | commitdiff |
2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | add hello world binary test |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | sort-of got binary execution test working |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | code-shuffle on testing to prepare loading large files... |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | ordering of tests for OP_ATTN needed shuffling. seems... |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | debugging termination (OP_ATTN) |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | update opcode map for OP_ATTN |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | debugging termination / OP_ATTN |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | add core start/stop capability, and OP_ATTN support |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | add in SPR test cases into test_issuer.py |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | add SPR test case, commented out for now |
tree | commitdiff |
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