Add proof for RegFile
[soc.git] / src /
2020-06-01 Michael NolanAdd proof for RegFile
2020-06-01 Luke Kenneth Casso... more unneeded fields from SR InputRecord
2020-06-01 Luke Kenneth Casso... remove data_len from SR input record
2020-06-01 Luke Kenneth Casso... remove zero/invert from ShiftRot Input Record
2020-06-01 Luke Kenneth Casso... add shift-rot input record and use it
2020-06-01 Luke Kenneth Casso... CompBROpSubset exists
2020-06-01 Luke Kenneth Casso... RS moved to port 1 (from port 3), remove need in ALU...
2020-06-01 Michael NolanAdd proof for RegFileArray
2020-06-01 Luke Kenneth Casso... remove use of reg3 in logical pipeline: CSV files moved...
2020-06-01 Michael NolanHave regfile use AnySeq instead of AnyConst
2020-06-01 Luke Kenneth Casso... rotator carry is set into both XER CA and CA32 fields
2020-06-01 Luke Kenneth Casso... comment out rlwinm. for now
2020-06-01 Luke Kenneth Casso... argh - need to zero the src_i input after "Read" is...
2020-06-01 Michael NolanEnable k-induction for register file proof
2020-06-01 Michael NolanThat was weird. For some reason it wasn't generating...
2020-06-01 Michael NolanFull BMC proof of Register
2020-06-01 Michael NolanBegin rewrite of proof_regfile.py
2020-06-01 Luke Kenneth Casso... put RB in 2nd position (matching immediate) in ShiftRot...
2020-06-01 Luke Kenneth Casso... sigh - another instance where write-mask needed to...
2020-06-01 Luke Kenneth Casso... remove xer so/ov, swap rs/rb to correct(?) order in...
2020-06-01 Tobias Platenproof_datamerger wip
2020-06-01 Luke Kenneth Casso... add rlwinm. test instruction (sets CR0)
2020-06-01 Luke Kenneth Casso... remove duplicate signal
2020-06-01 Luke Kenneth Casso... allow ALU / Logical ops to select RS as 1st operand
2020-06-01 Luke Kenneth Casso... allow M*-Form shiftrot to swap RS/RB back to consistent...
2020-06-01 Luke Kenneth Casso... add first version of ShiftRot CompUnit test
2020-06-01 Luke Kenneth Casso... shiftrot uses LogicalOutputData not ALUOutputData
2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
2020-06-01 Luke Kenneth Casso... add assertions for branch compunit output
2020-06-01 Luke Kenneth Casso... invert SPR1/2 in branch output data
2020-06-01 Luke Kenneth Casso... decode SPRs for branch
2020-06-01 Luke Kenneth Casso... swap over SPR1/2 to fit with microwatt SPR conventions
2020-06-01 Luke Kenneth Casso... add first version compunit branch test
2020-06-01 Luke Kenneth Casso... whoops need to read RS in CR inputs test
2020-06-01 Luke Kenneth Casso... add first version of CR CompUnit test
2020-06-01 Luke Kenneth Casso... minor adjustment, zero test in ALU output stage
2020-06-01 Luke Kenneth Casso... remove unneeded code
2020-05-31 Luke Kenneth Casso... bit-test on the function-unit value being tested
2020-05-31 Luke Kenneth Casso... add logical compunit test
2020-05-31 Luke Kenneth Casso... comment inputs and outputs from ALU unit test
2020-05-31 Luke Kenneth Casso... imports - use of globals. baaaad
2020-05-31 Luke Kenneth Casso... remove unneeded code and inputs. convert to "naming...
2020-05-31 Luke Kenneth Casso... split out common code from test_alu_compunit.py
2020-05-31 Luke Kenneth Casso... add comments for MultiCompUnit parallel test
2020-05-31 Luke Kenneth Casso... de-hard-code-ify getting results from MultiCompUnit
2020-05-31 Luke Kenneth Casso... remove unneeded imports
2020-05-31 Luke Kenneth Casso... split out compalu unit tests to separate module (gettin...
2020-05-31 Luke Kenneth Casso... HA! found a bug in MultiCompUnit handling of write...
2020-05-31 Luke Kenneth Casso... clarify
2020-05-31 Luke Kenneth Casso... OP_CMPEQB also requesting change of output reg (stop...
2020-05-31 Luke Kenneth Casso... OP_CMP is requesting a change of the output register...
2020-05-31 Luke Kenneth Casso... still investigating
2020-05-31 Luke Kenneth Casso... start with zero, try not to compare against 9 bytes...
2020-05-31 Luke Kenneth Casso... more debug statements
2020-05-31 Luke Kenneth Casso... add in more CR debug statements
2020-05-31 Luke Kenneth Casso... copy in cr0.data into cr0 temp, not whole of cr0 (inclu...
2020-05-31 Luke Kenneth Casso... remove commented-out vars from ALU input record
2020-05-31 Luke Kenneth Casso... write cr0 when op.write_cr.ok is set
2020-05-31 Luke Kenneth Casso... add write_cr to ALU record subset
2020-05-31 Luke Kenneth Casso... comment out xer ov/so for now
2020-05-30 Luke Kenneth Casso... get carry from cr write_cr
2020-05-30 Luke Kenneth Casso... select CR0 write out only when RC=1
2020-05-30 Luke Kenneth Casso... set CR0 output when OP_CMP or OP_CMPEQB need it
2020-05-30 Luke Kenneth Casso... add in use of "Settle"
2020-05-30 Luke Kenneth Casso... add in write-mask into MultiCompUnit and MCU-ALU unit...
2020-05-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-30 Tobias Platenunit test for DataMerger
2020-05-30 Luke Kenneth Casso... create read-mask for ALU CompUnit: switches off optiona...
2020-05-30 Luke Kenneth Casso... create a write-mask, anything with an "ok" in the Recor...
2020-05-30 Luke Kenneth Casso... allow MultiCompUnit outputs to be Records, to capture...
2020-05-30 Luke Kenneth Casso... add read-mask to MultiCompUnit
2020-05-30 Luke Kenneth Casso... code-shuffle / comments
2020-05-30 Luke Kenneth Casso... mess - but a functional mess. ALU-MultiCompUnit semi...
2020-05-30 Luke Kenneth Casso... grab other results from ALU pipeline in compunit test
2020-05-30 Luke Kenneth Casso... order of XER so/ca wrong way round from regspec
2020-05-30 Luke Kenneth Casso... still experimenting with ALU-CompUnit interaction
2020-05-29 Luke Kenneth Casso... interesting. use of Settle() works, showing that Regfi...
2020-05-29 Luke Kenneth Casso... module comments for popcount
2020-05-29 Luke Kenneth Casso... comments on popcount
2020-05-29 Luke Kenneth Casso... trigger ALU ready when operands ready
2020-05-29 Tobias Platenfixes for DataMerger
2020-05-29 Luke Kenneth Casso... trigger read ALU ready/valid from latch as well
2020-05-29 Luke Kenneth Casso... use a latch to communicate read/valid output from ALU
2020-05-29 Tobias PlatenDataMerger: rename addr_match_i to addr_array_i
2020-05-29 Tobias Platenfixed 'return m is missing'
2020-05-29 Tobias Platenwhitespace fixes
2020-05-29 Luke Kenneth Casso... latch all output on ALU output valid
2020-05-29 Luke Kenneth Casso... create read-done pulse
2020-05-29 Luke Kenneth Casso... write-release moves out of "ALU valid" due to using...
2020-05-29 Luke Kenneth Casso... signal start of request from when ALU triggers result...
2020-05-29 Luke Kenneth Casso... create rising pulse from ALU valid
2020-05-29 Luke Kenneth Casso... names of attributes needs to be dest_o not dest_i
2020-05-29 Luke Kenneth Casso... rename output signals in Test ALU
2020-05-29 Cesar StraussAllow immediate assertion of go in the same cycle as rel
2020-05-29 Cesar StraussCorrect typo
2020-05-29 Cesar StraussSend a one-clock "go" pulse after a configurable number...
2020-05-28 Luke Kenneth Casso... messing about with proof_regfile.py
2020-05-28 Luke Kenneth Casso... move simple_popcount out of class (does not use any...
2020-05-28 colepoirierAdded Initial() synchronous check with draft truth
2020-05-28 Luke Kenneth Casso... extra check on rd.req in test_alu_compunit
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