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bit of a hack to get test_mmu_dcache_pi.py operational.
[soc.git] / src /
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational. tree | commitdiff
2021-05-12 Luke Kenneth Casso... whitespace tree | commitdiff
2021-05-12 Luke Kenneth Casso... no need for sel0 tree | commitdiff
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1 tree | commitdiff
2021-05-11 Luke Kenneth Casso... connect MSR.PR to PortInterface in LDSTCompUnit tree | commitdiff
2021-05-11 Luke Kenneth Casso... add msr_pr bit in PortInterface tree | commitdiff
2021-05-11 Luke Kenneth Casso... add MSR to LD/ST Input Record tree | commitdiff
2021-05-11 Luke Kenneth Casso... comment tidyup tree | commitdiff
2021-05-11 Luke Kenneth Casso... must also pass through instruction fault exception... tree | commitdiff
2021-05-11 Luke Kenneth Casso... whoops names changed in MMU FSM tree | commitdiff
2021-05-11 Luke Kenneth Casso... tidyup comments and remove LoadStore COMPLETE state tree | commitdiff
2021-05-11 Luke Kenneth Casso... cleanup on exception setting tree | commitdiff
2021-05-11 Luke Kenneth Casso... rename LoadStore1 data structures back to microwatt... tree | commitdiff
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1 tree | commitdiff
2021-05-10 Luke Kenneth Casso... move LoadStore1 d_validblip setting, and get MMU_LOOKUP... tree | commitdiff
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py tree | commitdiff
2021-05-10 Tobias Platenstyle-wise: use ~self.instr_fault not self.instr_fault==0 tree | commitdiff
2021-05-10 Tobias PlatenLoadStore1: add rules for MMU_LOOKUP tree | commitdiff
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comments on translation of MMU_LOOKUP tree | commitdiff
2021-05-09 Luke Kenneth Casso... install MMU_LOOKUP vhdl to be translated to nmigen tree | commitdiff
2021-05-09 Luke Kenneth Casso... move (unused) ACK_WAIT code into FSM tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... remove invalid setting of d_in.valid from self.mmureq tree | commitdiff
2021-05-09 Luke Kenneth Casso... no SECOND_REQ tree | commitdiff
2021-05-09 Luke Kenneth Casso... remove SECOND_REQ tree | commitdiff
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py drive output d_in.valid tree | commitdiff
2021-05-09 Tobias Platenmove skeleton to elaborate tree | commitdiff
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py: add skeleton for fsm tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comment about LD/ST exception needs copying into... tree | commitdiff
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU tree | commitdiff
2021-05-09 Luke Kenneth Casso... add MMU bugtracker link tree | commitdiff
2021-05-09 Luke Kenneth Casso... git submodule update tree | commitdiff
2021-05-09 Luke Kenneth Casso... update code-comments tree | commitdiff
2021-05-09 Luke Kenneth Casso... add in alignment exception capture/reporting in LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... preference is to create a temp variable for comb and... tree | commitdiff
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase tree | commitdiff
2021-05-08 Luke Kenneth Casso... LoadStore1 tidyup tree | commitdiff
2021-05-08 Luke Kenneth Casso... transferring more over to LoadStore FSM tree | commitdiff
2021-05-08 Luke Kenneth Casso... start putting state info into LoadStore1, slowly puttin... tree | commitdiff
2021-05-08 Luke Kenneth Casso... add LoadStore State enum tree | commitdiff
2021-05-08 Luke Kenneth Casso... add bugreport link to mmu tree | commitdiff
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc... tree | commitdiff
2021-05-07 Luke Kenneth Casso... start setting DSISR bits but commented out tree | commitdiff
2021-05-07 Luke Kenneth Casso... update comments and docstrings tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops, import error tree | commitdiff
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops was still copying output over in CommonOutputStage tree | commitdiff
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that... tree | commitdiff
2021-05-07 Luke Kenneth Casso... move dsisr and dar into LoadStore1 tree | commitdiff
2021-05-07 Luke Kenneth Casso... move zero-dest-pred in Common Output Stage to not copy... tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops setup of core.sv_pred_sm/dm not indented and... tree | commitdiff
2021-05-06 Luke Kenneth Casso... whoops disabled tests agaaaaain tree | commitdiff
2021-05-06 Luke Kenneth Casso... pass relevant predicate mask bits through to Decoders... tree | commitdiff
2021-05-06 Luke Kenneth Casso... add in predicate mask bit detection when zeroing is... tree | commitdiff
2021-05-06 Luke Kenneth Casso... pass SVP64 ReMap field through to core and then on... tree | commitdiff
2021-05-06 Luke Kenneth Casso... moved exts* SVP64 unit tests to a different location tree | commitdiff
2021-05-06 Luke Kenneth Casso... if zeroing is set, put zero into input or output as... tree | commitdiff
2021-05-05 Tobias Platenfix bug in mmu/fsm.py tree | commitdiff
2021-05-05 Luke Kenneth Casso... put sv_input_record_layout onto CompOpSubsetBase after all tree | commitdiff
2021-05-05 Luke Kenneth Casso... whoops wrong signal name, set exc_happened tree | commitdiff
2021-05-05 Luke Kenneth Casso... add SVP64 RM fields to ALU input record tree | commitdiff
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py tree | commitdiff
2021-05-04 Luke Kenneth Casso... remove minerva debug unit (not needed) tree | commitdiff
2021-05-04 Jonathan Neuschäferminerva tests: Don't import soc.minerva.csr tree | commitdiff
2021-05-04 Luke Kenneth Casso... whoops disabled some test_issuer group tests tree | commitdiff
2021-05-04 Luke Kenneth Casso... add SVSTATE (SVSRR0) to TRAP pipeline tree | commitdiff
2021-05-04 Tobias Platenupate dsisr and dar using sync tree | commitdiff
2021-05-04 Luke Kenneth Casso... adding fast3 SPR to Trap pipeline and unit test tree | commitdiff
2021-05-04 Luke Kenneth Casso... new fast3 needs to be remapped to fast1 port in "reduce... tree | commitdiff
2021-05-04 Luke Kenneth Casso... missed that soc.regfile.util has moved to openpower... tree | commitdiff
2021-05-04 Luke Kenneth Casso... add SVSRR0 to FastRegsEnum tree | commitdiff
2021-05-04 Luke Kenneth Casso... add TODO comments and cross-reference to bug tree | commitdiff
2021-05-04 Luke Kenneth Casso... note a way to see if an exception happened, in TestIssuer tree | commitdiff
2021-05-04 Luke Kenneth Casso... add printout showing exception output from FUs tree | commitdiff
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience... tree | commitdiff
2021-05-04 Luke Kenneth Casso... wire in exc_o.happened into write-cancellation of LDSTC... tree | commitdiff
2021-05-04 Luke Kenneth Casso... comments, and change name of LDSTCompUnit exception_o... tree | commitdiff
2021-05-04 Luke Kenneth Casso... remove exception from data on FUBaseData, explicitly... tree | commitdiff
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit tree | commitdiff
2021-05-04 Luke Kenneth Casso... add LDSTException class to LDSTOutputData tree | commitdiff
2021-05-04 Luke Kenneth Casso... add option to add exception type to FUBaseData (pipe_data) tree | commitdiff
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData tree | commitdiff
2021-05-04 Luke Kenneth Casso... comment out nc (nocache), it seems to actually work tree | commitdiff
2021-05-03 Luke Kenneth Casso... MMU: get store to activate only when data is available... tree | commitdiff
2021-05-03 Luke Kenneth Casso... disable the cache for now, whilst testing read/write... tree | commitdiff
2021-05-02 Luke Kenneth Casso... use Const to define bit-length when comparing top nibbl... tree | commitdiff
2021-05-02 Luke Kenneth Casso... mmu FSM store in dcache: only put data onto d_in on... tree | commitdiff
2021-05-02 Luke Kenneth Casso... return d_out.valid instead of always "ok" in MMU FSM tree | commitdiff
2021-05-02 Luke Kenneth Casso... HACK WARNING: disable d-cache on hard-coded address... tree | commitdiff
2021-05-02 Luke Kenneth Casso... add nc argument to dcache load/store tests tree | commitdiff
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic... tree | commitdiff
2021-05-01 Luke Kenneth Casso... enable issuer_verilog.py to generate new MMU/DCache... tree | commitdiff
2021-05-01 Luke Kenneth Casso... send a DMI RESET at the end of the test. tree | commitdiff
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER... tree | commitdiff
2021-05-01 Luke Kenneth Casso... dcache store test: data goes in one cycle AFTER valid... tree | commitdiff
2021-05-01 Luke Kenneth Casso... only do dcache lookup for now tree | commitdiff
2021-05-01 Cesar StraussAdd GTKWave documents to each DCache unit test tree | commitdiff
2021-05-01 Luke Kenneth Casso... add LD/ST cases to MMU, which should all still work tree | commitdiff
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