| 2020-07-02 |
Luke Kenneth Casson... | comment out DIV unit for now
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | increase combinatorial stages to 8
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | reduce DIV radix to 1
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | add DIV function unit to compunits
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | add trap function unit into compunits
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | add bare wishbone option to TestIssuer, sort out ports
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | use single-arg pspec for TestIssuer and Core
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | first experimental index.rst for sphinx documentation
|
commit | commitdiff | tree |
| 2020-07-02 |
Luke Kenneth Casson... | add sphinx doc preliminary start
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | whoops missed some cases in unit test changing ALUHelpers
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | minor reorg on how Bus and Config classes are set up
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | whoops swapped trap test instructions accidentally
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | print out msr for debug
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | attempting to add SPRs to rfid test
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | add OP_SC
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | trap test check results
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | add name "test_issuer" to ilang conversion
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | add in trap compunit
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | add rfid and td/tw trap test
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | continue debugging trap pipeline
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | debugging trap pipeline
|
commit | commitdiff | tree |
| 2020-07-01 |
Luke Kenneth Casson... | start running trap unit test, fixing errors
|
commit | commitdiff | tree |
| 2020-06-30 |
Luke Kenneth Casson... | add lte ltu for use by twi and other trap functions
|
commit | commitdiff | tree |
| 2020-06-30 |
Luke Kenneth Casson... | add in pseudocode keyword into mdwn isa files
|
commit | commitdiff | tree |
| 2020-06-30 |
Luke Kenneth Casson... | code-morph on div pipeline
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | add README for fu directory
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | use correct ALUHelpers in div test
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | sort out syntax errors in div
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | first unit test for div
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | update submodule to fix div bug
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | add ignore for parsetab.py
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | add autogenerated do not commit comment
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | update submodule to div overflow
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | separate out divide by zero cases
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | update OV and OV32 ISACaller flags if overflow occurs
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | attempting to add overflow setting in ISACaller
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | whoops, hex parser digits are in multiples of 4 bits
|
commit | commitdiff | tree |
| 2020-06-29 |
Luke Kenneth Casson... | fetch instructions from bare wishbone fetch unit
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add cached fetch unit pass-through args
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | need args to WishboneArbiter, match data width size
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | read from instruction memory using FetchUnitInterface
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add Config Fetch interface and quick unit test
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add test instruction memory
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | add readonly option to TestMemory
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | expand instruction bus width to 64 bit, start on a...
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | parameterise minerva i-cache
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | got Pi2LSUI FSM working
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | sram address do not cut by LSBs
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | new Pi2LSUI working, using PortInterfaceBase
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | start new version of Pi2LSUI based on PortInterfaceBase
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | pass addr/mask through to PortInterfaceBase rd/wr addr
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | cleanup (remove unneeded imports)
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | more code-shuffle for TestMemoryPortInterface
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | more code-shuffle for TestMemoryPortInterface
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | minor cleanup, put get/set rdport/wrport into function
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | merge LDSTPort into TestMemoryPortInterface
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | use PortInterface connect_port
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | use PortInterface connect_port
|
commit | commitdiff | tree |
| 2020-06-28 |
Luke Kenneth Casson... | attempt to get Pi2LSUI FSM working
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | only activate ld_in_progress if addr is ok
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | make Memory accessible via TestSRAMBareLoadStoreUnit
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | increase (double) address width in TstL0CacheBuffer
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | increase (double) address width in TstL0CacheBuffer
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | unit test in l0_cache to connect to testpi and test_bare_wb
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | make PortInterface modules consistent with same API
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | use ConfigMemoryPortInterface in TstL0CacheBuffer
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | fix TestMemLoadStoreUnit, it required a FSM to monitor...
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | add wishbone Pi2LSUI test
|
commit | commitdiff | tree |
| 2020-06-27 |
Luke Kenneth Casson... | reconfigureable PortInterface testing now possible
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | name issue in Pi2LSUI
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whitespace and imports
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | slight reorg on test_pi2ls.py
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | correct address in pi2ls
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | oops forgot to initialise base class of TestMemLoadStoreUnit
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add in LenExpand shift/mask
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add quick test showing Pi2LSUI not quite reading/writing to
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | remove extraneous yields
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | set address ok and fix unit test to check it properly
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add pi.busy_o connection, increase to 64 bit
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | unit test broken is ok :)
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | set pi.ld.ok to 1 if pi.is_ld_i is set
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | load/store unit test needed to wait for busy_o
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whitespace
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | clean up output from BareLoadStoreUnit
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | halve the test memory size again
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | shrink test memory size down to only 64 words
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | investigating why write-enable not getting passed through
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | whoops forgot to call parent elaborate
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add test of SRAM through wishbone bus
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | code-morph which redirects lsmem unit test through...
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add a test SRAM that lives behind a minerva LoadStoreUnitInt...
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | dynamically specify wishbone layout (no longer hardcoded...
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | add reconfigureable Load/Store class
|
commit | commitdiff | tree |
| 2020-06-26 |
Luke Kenneth Casson... | extra parameterification of minerva LoadStoreUnits
|
commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | allow Pi2LSUI to accept incoming PortInterface and...
|
commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add extra parameter, mask_wid, to TestMemLoadStoreUnit
|
commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | start connecting up Pi2LSUI
|
commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add LenExpand module, tidyup on docstring
|
commit | commitdiff | tree |
| 2020-06-25 |
Luke Kenneth Casson... | add beginnings of Pi2LSUI
|
commit | commitdiff | tree |
| next |
projects / soc.git / search