rename ls180sram4k to ls180
[soclayout.git] / experiments9 / non_generated /
2021-04-18 Luke Kenneth Casso... rename ls180sram4k to ls180
2021-04-18 Luke Kenneth Casso... add full core variant including 4k sram of ls180
2021-04-18 Luke Kenneth Casso... update libresoc.v, c4m-jtag fsm was renamed
2021-04-18 Luke Kenneth Casso... update libresoc.v, c4m-jtag fsm was renamed
2021-04-10 Luke Kenneth Casso... use verilog for ls180 instead of ilang
2021-04-01 Luke Kenneth Casso... update / refresh full core DFF
2021-04-01 Luke Kenneth Casso... update / refresh full core DFF
2021-03-30 Luke Kenneth Casso... update 4k SRAM ls180.il
2021-03-29 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-29 Luke Kenneth Casso... aaagh found bug in litex setup, 64 bit WB bus was truncated
2021-03-28 Luke Kenneth Casso... reduce SPR regfile size considerably
2021-03-28 Luke Kenneth Casso... reduce INT and FAST regfile sizes by sharing ports
2021-03-27 Luke Kenneth Casso... hooray, corrected pinouts
2021-03-27 Luke Kenneth Casso... really weird error "unsupported direction for eint...
2021-03-22 Luke Kenneth Casso... increase DFF RAM size slightly
2021-03-22 Luke Kenneth Casso... add very small DFF srams variant
2021-03-22 Luke Kenneth Casso... create small dff with 4x 4k SRAMs
2021-03-22 Luke Kenneth Casso... ls180.il update
2021-03-22 Luke Kenneth Casso... argh pinmux generating bi-directional SDR DM when it...
2021-03-18 Luke Kenneth Casso... update ls180.il
2021-03-16 Luke Kenneth Casso... update ls180.il 4ksram with correct sdram connections
2021-03-14 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-11 Luke Kenneth Casso... try alternative pad/core connection
2021-03-06 Luke Kenneth Casso... add blackbox SPBlock 4k SRAM module
2021-03-05 Luke Kenneth Casso... remove sram 4k wb bte/cti
2021-03-05 Luke Kenneth Casso... litex expects wishbone "err" signals, added to sram 4k
2021-03-05 Luke Kenneth Casso... rename sram_4k wishbone interface to actually like...
2021-03-03 Luke Kenneth Casso... add blackbox attribute manually to SPBlock_512W64B8W
2021-03-02 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-02-20 Luke Kenneth Casso... increase core size to 50000 (DFF SRAMs)
2021-01-27 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2020-12-04 Luke Kenneth Casso... Revert "very weird bug where CoreToChip.buildChip canno...
2020-12-03 Luke Kenneth Casso... very weird bug where CoreToChip.buildChip cannot find...
2020-12-03 Luke Kenneth Casso... experiment adding 3x extra SRAMs back in but still...
2020-12-03 Luke Kenneth Casso... wtf does 32/64 bit bus have to do with gpio_o(8) disapp...
2020-12-03 Luke Kenneth Casso... reduce mem width due to yosys bugs. sigh
2020-12-03 Luke Kenneth Casso... added 3 more 4k SRAMs
2020-12-02 Luke Kenneth Casso... add full core back in
2020-11-14 Luke Kenneth Casso... update ls180 litex interfaces
2020-11-14 Luke Kenneth Casso... get rid of ibus/dbus/xics advanced wishbone tags
2020-11-14 Luke Kenneth Casso... update litex direction of iopads in ls180
2020-11-13 Luke Kenneth Casso... reduce nc ls180 pins to match
2020-11-13 Luke Kenneth Casso... fix clk_sel width (2 not 3)
2020-11-13 Luke Kenneth Casso... trying to get yosys to stop destroying pll_lck_o signal
2020-11-13 Luke Kenneth Casso... trying to get yosys to stop destroying pll_lck_o signal
2020-11-13 Luke Kenneth Casso... update full core ls180 (actually with litex peripherals...
2020-11-12 Luke Kenneth Casso... remove niolib io_in/out signal, no longer needed
2020-11-11 Luke Kenneth Casso... update CLKSEL / PLLOCK pins for ls180
2020-11-08 Luke Kenneth Casso... start conversion of ls180 to new niolib
2020-11-07 Luke Kenneth Casso... add io_in/io_out zero/one to help transition to new...
2020-11-07 Luke Kenneth Casso... messing about to get non_generated ls180.vst running...
2020-11-07 Luke Kenneth Casso... update full ls180 core
2020-10-04 Luke Kenneth Casso... match up power/gnd numbers with pinmux
2020-10-04 Luke Kenneth Casso... reduce number of not-connected
2020-10-02 Luke Kenneth Casso... add really cut down version of ls180.vst
2020-10-02 Luke Kenneth Casso... really really cut down core
2020-10-01 Luke Kenneth Casso... update to new ls180.il (no core yet) with PLL I/O and I2C
2020-09-30 Luke Kenneth Casso... add full core ilang file
2020-09-29 Luke Kenneth Casso... updated ls180 (no core, testing)
2020-09-28 Luke Kenneth Casso... cut out core for now to focus on ioring
2020-09-19 Luke Kenneth Casso... update ls180.il which successfully (except for 18 track...
2020-09-19 Luke Kenneth Casso... redo litex gateware
2020-09-19 Luke Kenneth Casso... first attempt putting in litex pins instead of bare...
2020-09-08 Luke Kenneth Casso... new version of test_issuer.il
2020-08-24 Luke Kenneth Casso... nuts. remove div pipe, use FSM
2020-08-24 Luke Kenneth Casso... update to latest test_issuer.il
2020-08-13 Luke Kenneth Casso... update to binary-addressed int regfile
2020-08-11 Luke Kenneth Casso... test_issuer.il with an alternative read/write port...
2020-08-11 Luke Kenneth Casso... use new "state" regfile
2020-08-05 Luke Kenneth Casso... add div and mul to test_issuer
2020-07-30 Luke Kenneth Casso... remove move unneeded signals from test_issuer.il
2020-07-30 Luke Kenneth Casso... stack of signals that should not have been connected...
2020-07-29 Luke Kenneth Casso... updated test_issuer.il to include new names
2020-07-21 Luke Kenneth Casso... new test_issuer.il, reducing fast regfile ports
2020-07-05 Luke Kenneth Casso... add SPR pipeline (but not DIV for now)
2020-07-02 Luke Kenneth Casso... name ALUs so as to not have to change cells.lst
2020-07-02 Luke Kenneth Casso... Revert "add div pipeline"
2020-07-02 Luke Kenneth Casso... add div pipeline
2020-07-02 Luke Kenneth Casso... update to new test_issuer.il, includes trap pipeline...
2020-06-30 Jean-Paul ChaputAdded experments9, a first taste at the full scale...